Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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50
Timer 0 MSB (TH0)
7 6 5 4 3 2 1 0 Reset Value
SFR 8Ch TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00h
TH0.7−0 Timer 0 MSB. This register contains the most significant byte of Timer 0.
bits 7−0
Timer 1 MSB (TH1)
7 6 5 4 3 2 1 0 Reset Value
SFR 8Dh TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00h
TH1.7−0 Timer 1 MSB. This register contains the most significant byte of Timer 1.
bits 7−0
Clock Control (CKCON)
7 6 5 4 3 2 1 0 Reset Value
SFR 8Eh 0 0 0 T1M T0M MD2 MD1 MD0 01h
T1M Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0
bit 4 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 1 uses a divide-by-12 of the crystal frequency.
1: Timer 1 uses a divide-by-4 of the crystal frequency.
T0M Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0
bit 3 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 0 uses a divide-by-12 of the crystal frequency.
1: Timer 0 uses a divide-by-4 of the crystal frequency.
MD2, MD1, MD0 Stretch MOVX Select. These bits select the time by which external MOVX cycles are to be stretched in the
bits 2−0 standard 8051 core. Since the MSC120x does not allow external memory access, these bits should be set to
000b to allow for the fastest Flash Data Memory access.
Memory Write Select (MWS)
7 6 5 4 3 2 1 0 Reset Value
SFR 8Fh 0 0 0 0 0 0 0 MXWS 00h
MXWS MOVX Write Select. This allows writing to the internal Flash Program Memory.
bit 0 0: No writes are allowed to the internal Flash Program Memory.
1: Writing is allowed to the internal Flash Program Memory, unless PML or RSL (HCR0, CADDR 3Fh) are set.