Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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5
ELECTRICAL CHARACTERISTICS: AV
DD
= 3V
All specifications from T
MIN
to T
MAX
, DV
DD
= +2.7V to +5.25V, f
MOD
= 15.625kHz, PGA = 1, Buffer ON, f
DATA
= 10Hz, ADC Bipolar Mode, and
V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted.
MSC120x
PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Input (AIN0-AIN5, AINCOM)
Analog Input Range
Buffer OFF AGND − 0.1 AV
DD
+ 0.1 V
Analog Input Range
Buffer ON AGND + 50mV AV
DD
− 1.5 V
Full-Scale Input Voltage Range (In+) − (In−), Bipolar Mode ±V
REF
/PGA V
Differential Input Impedance Buffer OFF 7/PGA
(1)
MΩ
Input Current Buffer ON 0.5 nA
Fast Settling Filter −3dB 0.469 • f
DATA
Bandwidth
Sinc
2
Filter −3dB 0.318 • f
DATA
Bandwidth
Sinc
3
Filter −3dB 0.262 • f
DATA
Programmable Gain Amplifier User-Selectable Gain Range 1 128
Input Capacitance Buffer ON 7 pF
Input Leakage Current Multiplexer Channel Off, T = +25°C 0.5 pA
Burnout Current Sources Buffer ON ±2 µA
ADC Offset DAC
Offset DAC Range ±V
REF
/(2•PGA) V
Offset DAC Resolution 8 Bits
Offset DAC Full-Scale Gain Error ±1.5 % of Range
Offset DAC Full-Scale Gain Error Drift 0.6 ppm/°C
System Performance
Resolution
MSC1200, MSC1201 24 Bits
Resolution
MSC1202 16 Bits
ENOB
MSC1200, MSC1201 22 Bits
ENOB
MSC1202 16 Bits
Output Noise See Typical Characteristics
No Missing Codes
MSC1200, MSC1201, Sinc
3
Filter,
Decimation > 360
24 Bits
No Missing Codes
MSC1202, Sinc
3
Filter 16 Bits
Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 % of FSR
Offset Error After Calibration 1.3 ppm of FS
Offset Drift
(2)
Before Calibration 0.1 ppm of FS/°C
Gain Error
(3)
After Calibration 0.005 %
Gain Error Drift
(2)
Before Calibration 0.5 ppm/°C
System Gain Calibration Range 80 120 % of FS
System Offset Calibration Range −50 50 % of FS
At DC, V
IN
= 0V 130 dB
Common-Mode Rejection
f
CM
= 60Hz, f
DATA
= 10Hz 130 dB
Common-Mode Rejection
f
CM
= 50Hz, f
DATA
= 50Hz 120 dB
f
CM
= 60Hz, f
DATA
= 60Hz 120 dB
Normal-Mode Rejection
f
SIG
= 50Hz, f
DATA
= 50Hz 100 dB
Normal-Mode Rejection
f
SIG
= 60Hz, f
DATA
= 60Hz 100 dB
Power-Supply Rejection At DC, dB = −20log(∆V
OUT
/∆V
DD
)
(4)
, V
IN
= 0V 88 dB
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
Calibration can minimize these errors.
(3)
The gain self-calibration cannot have a REF IN+ of more than AV
DD
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
(4)
∆V
OUT
is change in digital result.