Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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38
Table 6. Interrupt Summary
INTERRUPT
PRIORITY
INTERRUPT/EVENT
ADDR NUM
PRIORITY FLAG ENABLE
PRIORITY
CONTROL
AV
DD
Low Voltage Detect 33h 6
High
0
ALVDIP (AIPOL.1)
(1)
EALV (AIE.1)
(1)
N/A
Count (SPI/I
2
C) 33h 6 0 CNTIP (AIPOL.2)
(1)
ECNT (AIE.2)
(1)
N/A
I
2
C Start/Stop 33h 6 0 I2CIP (AIPOL.3)
(1)
EI2C (AIE.3)
(1)
N/A
Milliseconds Timer 33h 6 0 MSECIP (AIPOL.4)
(1)
EMSEC (AIE.4)
(1)
N/A
ADC 33h 6 0 ADCIP (AIPOL.5)
(1)
EADC (AIE.5)
(1)
N/A
Summation Register 33h 6 0 SUMIP (AIPOL.6)
(1)
ESUM (AIE.6)
(1)
N/A
Seconds Timer 33h 6 0 SECIP (AIPOL.7)
(1)
ESEC (AIE.7)
(1)
N/A
External Interrupt 0 03h 0 1 IE0 (TCON.1)
(2)
EX0 (IE.0)
(4)
PX0 (IP.0)
Timer 0 Overflow 0Bh 1 2 TF0 (TCON.5)
(3)
ET0 (IE.1)
(4)
PT0 (IP.1)
External Interrupt 1 13h 2 3 IE1 (TCON.3)
(2)
EX1 (IE.2)
(4)
PX1 (IP.2)
Timer 1 Overflow 1Bh 3 4 TF1 (TCON.7)
(3)
ET1 (IE.3)
(4)
PT1 (IP.3)
Serial Port 0 23h 4 5
RI_0 (SCON0.0)
TI_0 (SCON0.1)
ES0 (IE.4)
(4)
PS0 (IP.4)
External Interrupt 2 43h 8 6 IE2 (EXIF.4) EX2 (EIE.0)
(4)
PX2 (EIP.0)
External Interrupt 3 4Bh 9 7 IE3 (EXIF.5) EX3 (EIE.1)
(4)
PX3 (EIP.1)
External Interrupt 4 53h 10 8 IE4 (EXIF.6) EX4 (EIE.2)
(4)
PX4 (EIP.2)
External Interrupt 5 5Bh 11 9 IE5 (EXIF.7) EX5 (EIE.3)
(4)
PX5 (EIP.3)
Watchdog 63h 12 10
Low
WDTI (EICON.3) EWDI (EIE.4)
(4)
PWDI (EIP.4)
(1)
These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5).
(2)
If edge-triggered, cleared automatically by hardware when the service routine is vectored to. If level-triggered, the flag follows the state of the pin.
(3)
Cleared automatically by hardware when interrupt vector occurs.
(4)
Globally enabled by EA (IE.7).