Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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33
Slave Operation
Slave operation is supported, but address recognition,
R/W
determination, and ACK/NACK must be done under
software control. The Disable Clock Stretch (DCS) bit can
be set to disable clock stretching. When the DCS bit is set,
the device will no longer stretch the clock and will not
generate interrupts. This bit can be used to disable clock
stretch interrupts when there is no address match. This bit
is automatically cleared when a start or repeated start
condition occurs.
Transmit
Once address recognition, R/W determination, and
ACK/NACK are complete, the serial data to be transferred
can be written to I2CDATA. The data is automatically
shifted out based on the master SCL. After data
transmission, CNTIF is generated and SCL is stretched by
the MSC120x until the I2CDATA register is written with a
0xFFh. The ACK/NACK from the master can then be read.
Receive
Once address recognition, R/W determination, and
ACK/NACK are complete, I2CDATA must be written with
0xFFh to enable data reception. Upon completion of the
data shift, the MSC120x generates the CNT interrupt and
stretches SCL. Received data can then be read from
I2CDATA. After the serial data has been received,
ACK/NACK is generated by writing 0x7Fh (for ACK) or
0xFFh (for NACK) to I2CDATA. The write to I2CDATA
clears the CNT interrupt and clock stretch.
MEMORY MAP
The MSC120x contain on-chip SFR, Flash Memory,
Configuration Memory, Scratchpad SRAM Memory, and
Boot ROM. The SFR registers are primarily used for
control and status. The standard 8051 features and
additional peripheral features of the MSC120x are
controlled through the SFR. Reading from an undefined
SFR returns zero. Writing to undefined SFR registers is not
recommended and will have indeterminate effects.
Flash Memory is used for both Program Memory and Data
Memory; however, program execution can only occur from
Program Memory. Program/Data Memory partition size is
selectable. The partition size is set through HCR0 (in the
Configuration Memory), which is programmed serially.
Both Program and Data Flash Memory are erasable and
writable (programmable) in UAM. Erase and write timing
of Flash Memory is controlled in the Flash Memory Timing
Control register (FTCON, SFR 0EFh). As an added
precaution, a lock feature can be activated through HCR0,
which disables erase/write operation to 4kB of Program
Flash Memory or the entire Program Flash Memory in
UAM.
FLASH MEMORY
The page size for Flash memory is 64 bytes. The
respective page must be erased before it can be written to,
regardless of whether it is mapped to Program memory or
Data memory space. The MSC120x use a memory
addressing scheme that separates Program Memory
(FLASH/ROM) from Data Memory (FLASH/RAM).
Addressing of program and data segments can overlap
since they are accessed by different instructions.
The MSC120x have three hardware configuration
registers (HCR0, HCR1, and HCR2) that are
programmable only during Flash Memory Programming
mode.
The MSC120x allow the user to partition the Flash Memory
between Program Memory and Data Memory. For
instance, the MSC120xY3 contain 8kB of Flash Memory
on-chip. Through the hardware configuration registers, the
user can define the partition between Program Memory
(PM) and Data Memory (DM), as shown in Table 3,
Table 4, and Figure 20. The MSC120x families offer two
memory configurations.
Table 3. Flash Memory Partitioning
HCR0 MSC120xY2 MSC120xY3
DFSEL PM DM PM DM
00 2kB 2kB 4kB 4kB
01 2kB 2kB 6kB 2kB
10 3kB 1kB 7kB 1kB
11
(default)
4kB 0kB 8kB 0kB
Table 4. Flash Memory Partitioning Addresses
HCR0 MSC120xY2 MSC120xY3
DFSEL PM DM PM DM
00 0000−07FF 0400−0BFF 0000−0FFF 0400−13FF
01 0000−07FF 0400−0BFF 0000−17FF 0400−0BFF
10 0000−0BFF 0400−07FF 0000−1BFF 0400−07FF
11
(default)
0000−0FFF 0000 0000−1FFF 0000