Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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29
PLL
In PLL mode (HCR2, CLKSEL = 101 or HCR2,
CLKSEL = 100), the CPU can execute from an external
32.768kHz crystal. This mode enables the use of a PLL
circuit that synthesizes the selected clock frequencies
(PLL LF mode or PLL HF mode). If an external clock is
detected at startup, then the CPU begins execution in PLL
mode after startup. If an external clock is not detected at
startup, then the device reverts to the mode shown in
Table 2. The status of the PLL can be determined by first
writing the PLLLOCK bit (enable) and then reading the
PLLLOCK status bit in the PLLH SFR.
The frequency of the PLL is preloaded with default
trimmed values. However, the PLL frequency can be
fine-tuned by writing to the PLLH and PLLL SFRs. The
equation for the PLL frequency is:
PLL Frequency = ([PLLH:PLLL] + 1) • f
OSC
where f
OSC
= 32.768kHz.
The default value for PLL LF mode is automatically loaded
into the PLLH and PLLL SFRs.
For different connections to external clocks, see Figure 14,
Figure 15, and Figure 16.
For PLL HF mode, the value of PLL[9:0] is automatically
doubled in hardware; however, since PLL[9:0] is writable,
it can also be modified by writing to the respective SFRs.
XIN
XOUT
C
1
C
2
Refer to the crystal manufacturer’s specification
for C
1
and C
2
values.
NOTE:
Figure 14. External Crystal Connection
XINExternal Clock
Figure 15. External Clock Connection
XOUT
XIN
32pF
32pF
32.768kHz
NOTE: Typical configuration is shown.
Figure 16. PLL Connection