Datasheet

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SBAS317E − APRIL 2004 − REVISED MAY 2006
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28
CLOCKS
The MSC120x can operate in three separate clock modes:
Internal Oscillator mode (IOM), External Clock mode
(ECM), and Phase Lock Loop (PLL) mode. A block
diagram is shown in Figure 13. The clock mode for the
MSC120x is selected via the CLKSEL bits in HCR2. IO
low-frequency (LF) mode is the default mode for the
device.
Serial Flash Programming mode (SFPM) uses IO LF mode
(the HCR2 and CLKSEL bits have no effect). Table 2
shows the active clock mode for the various startup
conditions during User Application mode.
Internal Oscillator
In IOM, the CPU executes either in LF mode (if HCR2,
CLKSEL = 111) or high-frequency (HF) mode (if HCR2,
CLKSEL = 110 and DV
DD
= 5.0V). In this mode, XIN must
be grounded or tied to supply.
External Clock
In ECM (HCR2, CLKSEL = 011), the CPU can execute
from an external crystal, external ceramic resonator,
external clock, or external oscillator. If an external clock is
detected at startup, then the CPU will begin execution in
ECM after startup. If an external clock is not detected at
startup, then the device will revert to the mode shown in
Table 2.
100k
Ω
Internal
Oscillator
LF/HF
Mode
STOP
Phase
Detector
XIN
XOUT
Charge
Pump
VCO
PLL DAC
PLLDIV
SYSCLK
t
OSC
(1)
NOTE: (1) Disabled in PLL mode; therefore, an external resistor between XIN and XOUT is required.
t
PLL
/t
IOM
t
SYS
t
CLK
Figure 13. Clock Block Diagram
Table 2. Active Clock Modes
SELECTED CLOCK MODE HCR2, CLKSEL2:0 STARTUP CONDITION
(1)
ACTIVE CLOCK MODE (f
SYS
)
External Clock Mode (ECM)
010
Active clock present at XIN External Clock Mode
External Clock Mode (ECM) 010
No clock present at XIN IO LF Mode
Internal Oscillator Mode (IOM)
(2)
IO LF Mode 111 N/A IO LF Mode
Internal Oscillator Mode (IOM)
(2)
IO HF Mode 110 N/A IO HF Mode
PLL LF Mode
101
Active 32.768kHz clock at XIN PLL LF Mode
PLL
(3)
PLL LF Mode 101
No clock present at XIN Nominal 50% of IO LF Mode
PLL
(3)
PLL HF Mode
100
Active 32.768kHz clock at XIN PLL HF Mode
PLL HF Mode 100
No clock present at XIN Nominal 50% of IO HF Mode
(1)
Clock detection is only done at startup; refer to Serial Flash Programming Timing parameter t
RFD
in Figure 2.
(2)
XIN must not be left floating; it must be tied high or low or parasitic oscillation may occur.
(3)
PLL operation requires that both AV
DD
and DV
DD
are within their specified ranges.