Datasheet
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SBAS317E − APRIL 2004 − REVISED MAY 2006
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21
Furthermore, improvements were made to peripheral
features that off-load processing from the core, and the
user, to further improve efficiency. These iprovements
allow for 32-bit addition, subtraction and shifting to be
accomplished in a few instruction cycles, compared to
hundreds of instruction cycles executed through software
implementation. For instance, 32-bit accumulation can be
done through the summation register to significantly
reduce the processing overhead for multiple-byte data
from the ADC or other sources.
Family Device Compatibility
The hardware functionality and pin configuration across
the MSC120x families are fully compatible. To the user, the
only difference between family members is the memory
configuration. This design makes migration between
family members simple. Code written for the MSC1200Y2,
MSC1201Y2, or MSC1202Y2 can be executed directly on an
MSC1200Y3, MSC1201Y3, or MSC1202Y3, respectively.
(However, the ADC registers for the MSC1202 are mapped
differently than the MSC1200 or MSC1201.) This gives the
user the ability to add or subtract software functions and to
migrate between family members. Thus, the MSC120x
can become a standard device used across several
application platforms.
Family Development Tools
The MSC120x are fully compatible with the standard 8051
instruction set. This compatibility means that users can
develop software for the MSC120x with their existing 8051
development tools. Additionally, a complete, integrated
development environment is provided with each demo
board, and third-party developers also provide support.
Power-Down Modes
The MSC120x can power several of the on-chip
peripherals and put the CPU into Idle mode. This is
accomplished by shutting off the clocks to those sections,
as shown in Figure 6.
(see Figure 9)
USEC
FB
MSECH
HMSEC
FE
MSINT
FA
ACLK
F6
divide
by 64
MSECL
FD
FC
ms
µ
s
100ms
Flash Write
Timing
Flash Erase
Timing
WDTCON
SECINT
F9
FF
ADCON0
DC
FTCON
[3:0]
FTCON
[7:4]
EF
EF
seconds
interrupt
watchdog
f
DATA
f
SAMP
milliseconds
interrupt
ADC Output Rate
ADCON3 ADCON2
DF DE
Decimation Ratio
SPICON/
I2CCON
9A
C7
SCL/SCK
f
CLK
(30
µ
sto40
µ
s)
(5ms to 11ms)
PDCON.0
PDCON.1
Modulator Clock
PDCON.2
PDCON.3
IDLE
CPU Clock
Timers 0/1
SYSCLK
ADC Power Down
USART0
f
MOD
f
SYS
STOP
f
OSC
Figure 6. MSC120x Timing Chain and Clock Control