Datasheet

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SBAS317E APRIL 2004 − REVISED MAY 2006
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20
ENHANCED 8051 CORE
All instructions in the MSC120x families perform exactly
the same functions as they would in a standard 8051. The
effects on bits, flags, and registers are the same; however,
the timing is different. The MSC120x families use an
efficient 8051 core that results in an improved instruction
execution speed of between 1.5 and 3 times faster than the
original core for the same external clock speed (4 clock
cycles per instruction versus 12 clock cycles per
instruction, as shown in Figure 4). This efficiency
translates into an effective throughput improvement of
more than 2.5 times, using the same code and same
external clock speed. Therefore, a device frequency of
33MHz for the MSC120x actually performs at an
equivalent execution speed of 82.5MHz compared to the
standard 8051 core. This increased performance allows
the device to be tun at slower clock speeds, which reduces
system noise and power consumption, but provides
greater throughput. This performance difference can be
seen in Figure 5. The timing of software loops will be faster
with the MSC120x. However, the timer/counter operation
of the MSC120x may be maintained at 12 clocks per
increment or optionally run at 4 clocks per increment.
The MSC120x also provide dual data pointers (DPTRs).
Internal
ALE
Internal
PSEN
Internal
AD0AD7
Internal
A8−A15
ALE
PSEN
AD0AD7
PORT 2
CLK
Standard 8051 Timing MSC120x Timing
Single−Byte, Single−Cycle
Instruction
Single−Byte, Single−Cycle
Instruction
12 Cycles
4Cycles
Figure 5. Comparison of MSC120x Timing to
Standard 8051 Timing
Figure 4. Instruction Timing Cycle
f
CLK
instr_cycle
cpu_cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1
n+1 n+2