Datasheet

MM5483
SNLS368E –JULY 2000–REVISED MARCH 2013 www.ti.com
FUNCTIONAL DESCRIPTION
A block diagram for the MM5483 is shown in Figure 1 and a package pinout is shown in Figure 3. Figure 4
shows a possible 3-wire connection system with a typical signal format for Figure 4. Shown in Figure 5, the load
input is an asynchronous input and lets data through from the shift register to the output buffers any time it is
high. The load input can be connected to V
DD
for 2-wire control as shown in Figure 6. In the 2-wire control mode,
31 bits (or less depending on the number of segments used) of data are clocked into the MM5483 in a short time
frame (with less than 0.1 second there probably will be no noticeable flicker) with no more clocks until new
information is to be displayed. If data was slowly clocked in, it can be seen to “walk” across the display in the 2-
wire mode. An AC timing diagram can be seen in Figure 7. It should be noted that data out is not a TTL-
compatible output.
Figure 4. Three-Wire Control Mode
Figure 5. Data Format Diagram
Figure 6. Two-Wire Control Mode
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