Datasheet
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097C – JUNE 1980 – REVISED FEBRUARY 2002
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
IT+
Differential input high-threshold voltage V
O
= 2.7 V, I
O
= –0.4 mA 0.2 V
V
IT–
Differential input low-threshold voltage V
O
= 0.5 V, I
O
= –8 mA –0.2
†
V
V
IK
Enable-input clamp voltage I
I
= –10 mA –1.5 V
V
OH
High level out
p
ut voltage
V
ID
= 0.4 V, I
O
= –0.4 mA,
27
V
V
OH
High
-
level
output
voltage
ID
,
O
,
See Note 4 and Figure 1
2
.
7
V
V
OL
Low level out
p
ut voltage
V
ID
= –0.4 V, I
O
= 8 mA,
05
V
V
OL
Low
-
level
output
voltage
ID
,
O
,
See Note 4 and Figure 1
0
.
5
V
I
OZ
High im
p
edance state out
p
ut current
V
IL
= 0.8 V, V
ID
= –3 V, V
O
= 2.7 V 40
µA
I
OZ
High
-
impedance
-
state
output
current
V
IL
= 0.8 V, V
ID
= 3 V, V
O
= 0.5 V –40
µ
A
V
I
= –10 V –3.25
I
IB
Differential in
p
ut bias current
V
CC
= 0 V or 5.25 V,
V
I
= –3 V –1.5
mA
I
IB
Differential
-
input
bias
current
CC
,
Other inputs at 0 V
V
I
= 3 V 1.5
mA
V
I
= 10 V 3.25
I
IH
High level enable in
p
ut current
V
I
= 5.25 V 100
µA
I
IH
High
-
level
enable
input
current
V
I
= 2.7 V 20
µ
A
I
IL
Low-level enable input current V
I
= –0.5 V –100 µA
I
OS
Short-circuit output current V
ID
= 3 V, V
O
= 0, See Note 5 –15 –100 mA
I
CC
Supply current V
IL
= 0 85 mA
†
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for threshold
voltages only.
NOTES: 4. Refer to ANSI Standards TIA/EIA-422-B and TIA/EIA-423-B for exact conditions.
5. Only one output should be shorted at a time.
switching characteristics, V
CC
= 5 V, C
L
= 15 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PHL
Propagation delay time, high- to low-level output
See Figure 2
28 35 ns
t
PLH
Propagation delay time, low- to high-level output
See
Figure
2
27 30 ns
t
PZH
Output enable time to high level 13 30 ns
t
PZL
Output enable time to low level
See Figure 3
20 30 ns
t
PHZ
Output disable time from high level
See
Figure
3
26 35 ns
t
PLZ
Output disable time from low level 27 35 ns