Datasheet

Capacitor Selection
ESD Protection
ESD Test Conditions
Human-Body Model (HBM)
-
+
DUT
R
D
1.5 kW
V
HBM
100 pF
C
S
MAX208
SLLS596C – OCTOBER 2003 – REVISED AUGUST 2009 ................................................................................................................................................ www.ti.com
The capacitor type used for C1 – C4 is not critical for proper operation. The MAX208 requires 0.1- µ F capacitors,
although capacitors up to 10 µ F can be used without harm. Ceramic dielectrics are suggested for the 0.1- µ F
capacitors. When using the minimum recommended capacitor values, ensure that the capacitance value does
not degrade excessively as the operating temperature varies. If in doubt, use capacitors with a larger (e.g., 2 × )
nominal value. The capacitors' effective series resistance (ESR), which usually rises at low temperatures,
influences the amount of ripple on V+ and V – .
Use larger capacitors (up to 10 µ F) to reduce the output impedance at V+ and V – .
Bypass V
CC
to ground with at least 0.1 µ F. In applications sensitive to power-supply noise generated by the
charge pumps, decouple V
CC
to ground with a capacitor the same size as (or larger than) the charge-pump
capacitors (C1 to C4).
TI MAX208 devices have standard ESD protection structures incorporated on the pins to protect against
electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver
outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures
were designed to successfully protect these bus pins against ESD discharge of ± 15 kV when powered down.
ESD testing is stringently performed by TI, based on various conditions and procedures. Please contact TI for a
reliability report that documents test setup, methodology, and results.
The HBM of ESD testing is shown in Figure 5 , while Figure 6 shows the current waveform that is generated
during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage
of concern and subsequently discharged into the DUT through a 1.5-k Ω resistor.
Figure 5. HBM ESD Test Circuit
8 Submit Documentation Feedback Copyright © 2003 – 2009, Texas Instruments Incorporated
Product Folder Link(s): MAX208