Datasheet

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© National Semiconductor Corporation 2009 Printed in U.S.
10
Rx Board
Configuration Settings
Component Name Function
Power Connections
J11 5V DC Optional 5V DC Power Jack. Note: unpopultated by default
J8 1.8V DC 1.8V VDD Power.
JP13 3.3V DC 3.3V VDD Power (left header pin), ground (right header pin)
J9 VSS Ground.
JP12 VDDIO Output voltage select. Jumper set to 3.3V by default.
Input and Output Connections
J7
44 position wall
header (ROUT0 –
ROUT20, PCLK)
Connect to data output.
JP6 – JP9 GPI0 – GPI3 Optional general purpose back channel data input
J3 and J4 SMA Connector Connect to Channel Link II input. Note: unpopulated by default.
J2
USB Connector
(micro-B, female)
Connect to Channel Link II input.
Control Connections
S1:1
RESO Reserved. Keep set to LOW.
S1:2 M_S
I2C Mode Select.
M_S = H, Slave mode – device will accept a clock from a local master
M_S = L, Master mode – device will generate a clock and drive a slave device
S1:3 BISTEN
BIST Enable
BISTEN = H, BIST mode enabled
BISTEN = L, BIST mode disabled (default)
S1:4 PDB
Power down mode input.
PDB = H, Deserializer is enabled (default)
PDB = L, Deserializer is in power-down mode
JP4 and VR1 CAD
Connect CAD pin to VSS to have the default device PHY address (default setting).
Connect CAD pin to VR1 pin; then adjust VR4 value to select desired device PHY address.
See datasheet for detailed information.
J6 and JP5 I2C Interface Leave JP9 unconnected if I2C VDD is provided by an external source. (default).
Others
LED1 PASS PASS output. “ON” when PASS is “H”
LED2 LOCK LOCK output. “ON” when LOCK is “H”
JP3, JP2 Other options Do not connect