Datasheet

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© National Semiconductor Corporation 2009 Printed in U.S.
3
Tx Board Configuration Settings
Component Name Function
Power Connections
J2 5V DC Optional 5V DC Power Jack.
J3 1.8V DC 1.8V VDD Power.
JP1 3.3V DC 3.3V VDD Power (left header pin) and Ground (right header pin)
J4 VSS Ground.
JP2 VDDI
Connect to 3.3V for 3.3V input logic levels and I2C interface. Connect to 1.8V for 1.8V
input logic levels and no I2C.
JP18 VDDL Always connect to 1.8V.
JP23 VDDP Always connect to 1.8V.
JP24 VDDHS Always connect to 1.8V.
Input and Output Connections
J1
28 position wall
header LVCMOS parallel clock and data input.
J7 and J8 SMA Connectors
Channel Link II output.
(When using these connectors, R49 and R50 should be placed with 0Ω resistors, the
traces to the P1 should be cut).
P3 USB Connector Channel Link II output.
JP25 and JP26
Power Wire in USB
cable through P3 Connect to VSS is recommended.
Control Connections
SW1: 7 RFB
Set to “L” to strobe the input data on the falling clock edge.
Set to “H” to strobe the input data on the rising clock edge.
SW1: 6 PDB
Set to “L” for the power down mode.
Set to “H” for the normal operation.
SW1: 5 CONFIG0
Set to “L” to interface with a DS82LV2422 or DS92LV0422.
See datasheet for reverse compatibility mode information
SW1: 4 CONFIG1
Set to “L” to interface with a DS82LV2422 or DS92LV0422.
See datasheet for reverse compatibility mode information
SW1: 3 BISTEN
Set to “H” for the BIST enable mode.
Set to “L” for normal operation.
See datasheet for detail information.
SW1: 2 VODSEL
Connect to “L” for low output VOD swing.
Connect to “H” for high output VOD swing.
See datasheet for more information.
SW1: 1 RES2 Keep RES2 set to “L”
JP10 and VR4 ID[x]
Connect JP19 to VSS to have the default device PHY address (h’EC).
Connect JP19 to VR4; then adjust VR4 value to select desired device PHY address. See
datasheet for detail information.
JP3 and J6 I2C Interface Connect JP3 if the I2C power is not supplied on J6. Otherwise, leave it unconnected.