Datasheet

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© National Semiconductor Corporation 2009 Printed in U.S.
10
Rx Board Configuration Settings
Component Name Function
Power Connections
J7 5V DC Optional 5V DC Power Jack.
J4 1.8V DC 1.8V VDD Power.
JP1 3.3V DC 3.3V VDD Power (left header pin) and Ground (right header pin)
J5 VSS Ground.
JP2 VDDIO
Connect to 3.3V for 3.3V input logic levels and I2C interface. Connect to 1.8V for 1.8V
input logic levels and no I2C.
Input and Output Connections
P1
28 position wall
header
LVCMOS parallel data output.
J3 and J4 SMA Connector
Channel Link II input. (optional)
(When using these connectors, R53 and R54 should be placed with 0Ω resistors, the
traces to the J1 should be cut).
J2 USB Connector Channel Link II input. (default)
JP11 and JP12
Power Wire in USB
cable through J2
Connect to VSS is recommended.
P2 USB Connector Optional Channel Link II loop through driver output.
Control Connections
S1: 3 BISTEN
Set to “H” for the BIST enable mode.
Set to “L” for normal operation.
See datasheet for detail information.
S1: 2 RES0 Keep RES0 set to “L"
S1: 1 PDB
Set to “L” for the power down mode.
Set to “H” for the normal operation.
JP24 and VR3 ID[x]
Connect JP19 to VSS to have the default device PHY address (h’EC).
Connect JP19 to VR4; then adjust VR4 value to select desired device PHY address. See
datasheet for detail information.
J3 and JP23 I2C Interface Connect JP3 if the I2C power is not supplied on J6. Otherwise, leave it unconnected.
Strap Pin Configuration Options
R[1:28], R41, R42 --
Populate with 10k ohm resistor to enable desired strap option. See datasheet for details on
strap options.
Others
LED1 PASS
PASS output. “ON” when PASS is “H”.
See datasheet for detail information.
LED2 LOCK
LOCK output. “ON” when LOCK is “H”.
See datasheet for detail information.
JP11, JP25, JP26 Other options Do not connect