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LV24EVK01

Channel Link II Ser/Des

Evaluation Kit

Rev 0.3

Aug, 2010

General Description

The LV24EVK01 is designed to allow for easy evaluation of the DS92LV2421 and DS92LV2422 Channel Link II Ser/Des. This

kit allows for 2 basic methods of evaluation:

1) Users may apply parallel clock and data, and evaluate the power, jitter and cable performance of the Ser/Des. Or,

2) Apply only a parallel clock and enable BIST mode. This allows the user to easily evaluate the serial link and check

device feature functionality such as transmit de-emphasis, receive equalization, SSCG, etc.

The LV24EVK01 boards uses USB connectors as the serial Channel Link II inputs/outputs. SMA connectors can also be

attached and configured for serial input/output if other types of the cable are desired.

Features

• 10 – 75 MHz support for 240 Mbps – 1.8 Gbps application payload (280 Mbps to 2.1 Gbps Serial Link)

• LVCMOS parallel interface: 24-bit data + 3 low speed control + clock

• RGB888 + VS, HS, DE serialized to 1 pair

• AC Coupled STP Interconnect up to 10 meters in length

• Selectable output VOD, adjustable de-emphasis and receive equalization

• Integrated serial terminations

• @ Speed link BIST Mode and reporting pin

• Optional I2C compatible Serial Control Bus

• Power down mode minimizes power dissipation

• Randomized, DC-balanced and Scrambled data stream

• >8 kV HBM

• Backward compatible mode for operation with older generation devices

Applications

• Industrial Displays

• Machine Vision

• Medical Imaging

Ordering Information

PART: LV24EVK01

Demo boards:

Tx: DS92LV2421-EVK

national.com

Rx: DS92LV2422-EVK

Summary of content (17 pages)

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LV24EVK01 Channel Link II Ser/Des Evaluation Kit Rev 0.3 Aug, 2010 General Description The LV24EVK01 is designed to allow for easy evaluation of the DS92LV2421 and DS92LV2422 Channel Link II Ser/Des. This kit allows for 2 basic methods of evaluation: 1) Users may apply parallel clock and data, and evaluate the power, jitter and cable performance of the Ser/Des. Or, 2) Apply only a parallel clock and enable BIST mode.
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Typical Application Configuration Quick Start Guide: DS92LV2421 Tx Board: 1. Connect 3.3V DC power to the left header pin of JP1 and ground to the right header pin of JP1 of the board. Connect 1.8V DC power to J3 and ground to J4. By default JP2 is configured such that VDDIO = 3.3 V. 2. Attach the USB cable to the TX board (DS92LV2421) output and to an RX board (DS992LV2422 supplied) input. The default cable connector on the TX board is P3, which is mounted to the bottom of the evaluation board. 3.
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Tx Board Configuration Settings Component Name Function Power Connections J2 5V DC Optional 5V DC Power Jack. J3 1.8V DC 1.8V VDD Power. JP1 3.3V DC 3.3V VDD Power (left header pin) and Ground (right header pin) J4 VSS JP2 VDDI Ground. Connect to 3.3V for 3.3V input logic levels and I2C interface. Connect to 1.8V for 1.8V input logic levels and no I2C. JP18 VDDL Always connect to 1.8V. JP23 VDDP Always connect to 1.8V. JP24 VDDHS Always connect to 1.8V.
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Tx Board Bill of Materials Item Qty Reference 1 2 3 4 2 2 4 2 5 7 6 7 2 2 8 6 9 10 11 5 1 3 12 5 13 5 C1,C15 C16,C2 C3,C4,C8,C9 C5,C6 C7,C14,C20,C23,C 24,C28, C30 C10,C13 C11,C12 C17,C18,C21,C31, C32,C33 C19,C25,C26,C27, C29 C22 JP1,JP3,JP5 JP2,JP10,JP13,JP1 4,JP15 JP4,JP6,JP7,JP8,J P9 14 2 JP12,JP111 15 1 JP16 16 1 J1 17 18 1 2 J2 J3,J4 19 1 J5 Part MFR MFR Part# Digi-Key Part# 2.2uF 0.1uF 10uF_open 0.
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27 1 R1 1.50K Panasonic R2,R38,R44,R 0 54,R55 Ohm,0402_open Panasonic ERJ-2RKF1501X P1.50KLCT-ND ERJ2GEJ0R00X_open P0.0JTR-ND_open 28 5 29 29 R3,R4,R5,R6,R 7,R8,R9,R10, 49.9ohm_open R11,R12,R13, R14,R15,R16, R17,R18,R19, R20,R21,R22, R23,R24,R25, R26,R27,R28, R29,R34,R35 Panasonic ERJ1GEF49R9C_open P49.9ABCT-ND_open 30 1 R30 49.9ohm_open R31,R32,R33, R45,R46,R47, 0 Ohm,0402 R48,R53,R56, R57 Panasonic ERJ6ENF49R9V_open P49.9CCT-ND_open 31 10 Panasonic ERJ-2GEJ0R00X P0.
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VDDI G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 RES2 49 37 38 39 40 41 42 43 44 45 46 47 48 S1 VSS R57 PDB VSS L H VSS DI10 DI11 DI12 DI13 DI14 DI15 DI16 DI17 DI18 DI19 DI20 DI21 C33 22uF VSS + RFB PDB CONFG0 CONFG1 BISTEN VODSEL RES2 VSS G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 U1 VDDIc DS92LV2421 SDA SCL PDB R55 0 Ohm,0402_open VDDTXc VSS C22 1 2 VSS I2S0 I2S1 VODSEL DeEmph VDDTX PDB DOUT+ DOUT RES2 VDDHS RES1 RES0 VDDP CONFG[1] BISTEN R54 0 Ohm,0402_open RFB CONFG0 VDDLc VD D I R4
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national.com © National Semiconductor Corporation 2009 7 Printed in U.S. VSS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 HS VS DE PCLK VSS Tuesday , May 18, 2010 Date: Sheet DS92LV2421 Tx Demo Board - Parallel Input Document Number DS92LV2421 Tx Demo Board Size A Title 0201 R3 49.9ohm_open 0201 R4 49.9ohm_open 0201 R5 49.9ohm_open 0201 R6 49.9ohm_open 0201 R7 49.9ohm_open 0201 R8 49.
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Printed in U.S. 1 BANANA J4 BANANA C15 + 2.2uF 1 C13 + 22uF 2 1 3 5 7 OPTION AL 5V IN PU T POW ER C ONN EC TOR 1 2 3 CONN JACK PWR_open J2 2x4 pin Jumper_open VSS J5 2 4 6 8 C4 1 + C9 VSS VDD C8 0.1uF C16 + 1 2 DIRECT 1.8V INPUT POWER CONNECTOR J3 1 1 2 !!!WARNING!!! Input power thru J2 OR J3 OR J4 ONLY!! Input power thru only one connector!! VSS 1 + VSS VSS + C3 + VSS 1.8V VD D R41 3 INPUT 82.5oh 2 m_open Tab/Vout OUTPUT 1 ADJ/GND 4 1 2 10uF_open 2 10uF_open 3.
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Tx Board Reference Layout Top Layer national.com © National Semiconductor Corporation 2009 Bottom Layer 9 Printed in U.S.
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Rx Board Configuration Settings Component Name Function Power Connections J7 5V DC Optional 5V DC Power Jack. J4 1.8V DC 1.8V VDD Power. JP1 3.3V DC 3.3V VDD Power (left header pin) and Ground (right header pin) J5 VSS JP2 VDDIO Input and Output Connections 28 position wall header P1 Ground. Connect to 3.3V for 3.3V input logic levels and I2C interface. Connect to 1.8V for 1.8V input logic levels and no I2C. LVCMOS parallel data output. Channel Link II input.
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Rx Board Bill of Materials Part Item Qty Reference MFR ______________________________________________ 1 2 3 4 5 6 7 8 9 10 11 12 13 Digi-Key Part# 4 C1,C2,C9,C10 10uF_open 6 C3,C7,C21,C2 0.1uF C4,C8,C22,C2 0.01uF 5 5,C31 4 C5,C6,C15,C1 0.1uF 22uF 2 C11,C14 2.2uF 2 C12,C17 0.
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28 29 30 31 32 33 34 35 36 37 P1 HEADER 28x2 P2 USB A_open R1,R2,R3,R4,R 10Kohm_open 30 5,R6,R7,R8, R9,R10,R11,R1 2,R13,R14, R15,R16,R17,R 18,R19,R20, R21,R22,R23,R 24,R25,R26, R27,R28,R41,R 42 R29,R30,R53,R 0 ohm_open 4 54 R31,R37,R38,R 10K 4 39 100K_open 1 R32 0 Ohm,0402_open 1 R33 82.
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J2 mini USB 5pin VD D JP12 VDDIOc VDD 1 2 3 4 5 JP11 VDDIO RIN+_USB RIN-_USB VSS mini B: component side (BOTTOM) VSS 5 mini USB 5pin_open 4 3 2 1 J10 1 2 3 4 5 VSS S1 VSS L H VDDIRc 1 C6 VSS 22uF C19 + BISTEN RES_0 PDB CMLOUTP VSS 0.1uF 2 VSS VDDIRc VSS R43 JP16 1 2 IDx VSS VDDRc 2 CMLOP CMLON VSS VR3 J3 0.1uF VSS C34 VDDIO VDD_I2C VSS 2 - VSS P2 1 2USB A_open 3 4 VSS VSS 13 Printed in U.S. 5pF 5pF VSS C36 C35 R62 4.7K 0603 VSS VDD_I2C SDA SCL R61 4.
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R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 HS VS DE PCLK VSS VD D IOc R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 HS VS DE PCLK VSS VDDIOc PASS PASS 0201 R42 10Kohm_open 14 Printed in U.S.
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Printed in U.S. 1 1 BANANA J5 1 C17 + 2.2uF 2 1 C14 + 22uF 2 1 3 5 7 OPTION AL 5V IN PU T POW ER C ONN EC TOR 1 2 3 CONN JACK PWR_open J7 2x4 pin Jumper_open VSS J6 2 4 6 8 VSS VDD VDD1.8V 0.1uF C18 + 1 2 BANANA + C10 + VSS VD D VDD3.3V VSS + C1 + 10uF_open 10uF_open C2 3.3V 10uF_open 10uF_open C9 1 2 1 2 J4 1 VSS R34 3 INPUT 82.5ohm_open 2 Tab/Vout OUTPUT 1 ADJ/GND 4 2 1 2 U2 U3 2 JP1 OPTIONAL Exte rnal 3.3V input. OPTION AL 5V to 3.
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Rx Board Reference Layout Top Layer national.com © National Semiconductor Corporation 2009 Bottom Layer 16 Printed in U.S.
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