Datasheet

V
IN
V
OUT
1 M:
R
ISO
1 M:
C
L
+
-
I
SEL
10 100 1000
CAPACITIVE LOAD (pF)
0
30
70
PHASE MARGIN (°)
10
20
40
50
60
LOW POWER MODE
FULL POWER MODE
MID POWER MODE
R
L
=100 k:
LPV531
SNOSAK5B MARCH 2006REVISED MARCH 2013
www.ti.com
When the power setting of the LPV531 is reduced, both the transconductance of the input stage and the
transconductance of the output stage will scale lineary with the power level to lower levels. This means that both
the unity gain frequency and the pole to the transconductance of the output stage and the load capacitance will
move down. Because both the unity gain frequency and the output pole move down in similar amounts, the
stability of the LPV531 is still the same. This is shown in Figure 41 which gives the phase margin as a function of
the load capacitance in the low power mode (5 µA), mid-power mode (40 µA) and high power mode (400 µA).
Though the power level and unity gain frequency move with about two decades, the phase margin as a function
of the capacitive load is hardly affected. This means that when the LPV531 is stable in an application circuit with
a given load capacitance in the high power mode, the circuit will remain stable with the same capacitive load
connected when the power level is reduced.
Figure 41. Phase Margin vs. Capacitive Load
Figure 42 shows a method that is sometimes used to allow an op amp to drive larger capacitors than it was
originally designed to do. The capacitive load is isolated from the output of the op amp with an isolation resistor
(R
ISO
). This moves the output pole, that was originally located at g
m,out
/C
l
, to a higher frequency. This method
requires that the value of R
ISO
is in the same order of magnitude as 1/g
m,out
. For the LPV531, this method will not
be effective when used across a broad range of power levels. This is because the high power mode will require a
relatively small value for R
ISO
, while such a small R
ISO
will be ineffective at low power levels. In most applications
this should not be a problem as the LPV531 can drive sufficient capacitive loads without the need for an external
isolation resistor.
Figure 42. Compensation by Isolation Resistor
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