Datasheet

0 1.0
2.0
_
3.0
_
4.0
_
5.0
_
CAP VALUE (% OF NOM. 1 uF)
DC BIAS (V)
100%
80%
60%
40%_
20%
_
0402, 6.3V, X5R
0603, 10V, X5R
LP5996
SNVS415C –NOVEMBER 2006–REVISED MAY 2013 www.ti.com
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be
suitable in the actual application.
Figure 20. Graph Showing a Typical Variation in Capacitance vs DC Bias
The capacitance value of ceramic capacitors varies with temperature. The capacitor type X7R, which operates
over a temperature range of -55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type
X5R has a similar tolerance over a reduced temperature range of -55°C to +85°C. Many large value ceramic
capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47µF to 4.7µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.
ENABLE CONTROL
The LP5996 features active high enable pins for each regulator, EN1 and EN2, which turns the corresponding
LDO off when pulled low. The device outputs are enabled when the enable pins are set to high. When not
enabled the regulator output is off and the device typically consumes 2nA.
If the application does not require the Enable switching feature, one or both enable pins should be tied to V
IN
to
keep the regulator output permanently on.
To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and
below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under V
IL
and V
IH
.
BYPASS CAPACITOR
The internal voltage reference circuit of the LP5996 is connected to the C
BYP
pin via a high value internal resistor.
An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs
of the device. There is also some improvement in PSSR and line transient performance. Internal circuitry ensures
rapid charging of the C
BYP
capacitor during start-up. A 10nF, high quality ceramic capacitor with either NPO or
COG dielectric is recommended due to their low leakage characteristics and low noise performance.
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