Datasheet

LP5900
0.47 PF
(B2)
(B1)
(A1)
0.47 PF
(A2)
V
OUT
GND
V
IN
V
EN
V
IN
sense
V
OUT
sense
C
IN
C
OUT
V
IN
V
OUT
V
EN
GND
Schematic Diagram www.ti.com
4 Schematic Diagram
The evaluation board schematic is shown in Figure 1.
Figure 1. Evaluation Board Schematic
5 PCB Layout
The layout of the evaluation board is shown in Figure 2.
Figure 2. Evaluation Board Component and Pin Layout Board Size:- 21mm x 21mm
2
AN-1396 LP5900 DSBGA Evaluation Board Information SNVA123C–September 2005–Revised April 2013
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