Datasheet

8
6
5
7
1
3
4
2
V
OUT
V
IN
GND
DELAY
C
BYP
SENSE
SD
ERROR
V
REF
POR
+
-
V
IN
C
BYP
GND
DELAY
V
OUT
2.2 PA
+
-
SENSE
SD
ERROR
1.2V
6 M:
RFB2
RFB1
0.5V
OFF
ON
LP3997
SNVS272B –MAY 2004–REVISED MAY 2013 www.ti.com
Functional Block Diagram
Pin Descriptions
Pin No. Name Description
1 C
BYP
Noise bypass pin. For low noise applications a 0.1µF or larger ceramic capacitor should be connected from
this pin to ground. This will also improve PSSR.
2 DELAY A capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (pin
7) output. See Applications Information.
3 GND Ground pin. Local ground for C
BYP
,C
IN
, C
OUT
and C
DELAY
.
4 V
IN
Input supply pin. Connect C
IN
between this pin and GND.
5 V
OUT
Output voltage, Connect C
OUT
between this pin and ground.
6 SENSE Connect this pin to V
OUT
(pin 5). For best performance the connection should be made as close to the load
as possible.
7 ERROR This open drain output is an error flag output which goes low when V
OUT
drops 5% below its nominal
voltage. This pin also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.
8 SD Shutdown. Disables the regulator when less than 0.4V is applied. Enables the regulator when greater than
0.9V. The Shutdown pin is pulled down internally by a 6MΩ resistor.
Connection Diagram
8-Lead VSSOP
Package Number DGK
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