Datasheet
Bottom View Top View
B1A1
B2A2
V
IN
V
OUT
V
EN
GND
B1 A1
B2 A2
V
IN
V
OUT
V
EN
GND
LP3991
SNVS296H –DECEMBER 2006–REVISED MAY 2013
www.ti.com
PIN DESCRIPTIONS
Pin No. Symbol Name and Function
B1 V
OUT
Voltage output. A Low ESR Ceramic Capacitor should be connected from this pin to GND.
(See Application Information)
Connect this output to the load circuit.
A1 GND Common Ground. Connect to Pad.
A2 V
EN
Enable Input; Enables the Regulator when ≥ 0.95V.
Disables the Regulator when ≤ 0.4V.
Enable Input has an internal 1.2MΩ pull-down resistor to GND.
B2 V
IN
Voltage Supply Input. A 1.0µF capacitor should be connected from this pin to GND.
Connection Diagram
Figure 1. 4 Bump Thin DSBGA, Large Bump
See Package Number YZR0004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3991