Datasheet

www.ti.com Pin Description 5 × 5 Package
5 Pin Description 5 × 5 Package
Pin # Name I/O
(1)
Type
(1)
Description
1 PKEY I D CPU Wakeup Input
2 nTJ I D CPU Wakeup Input
3 SP I D CPU Wakeup Input
4 EXT_WAKEUP O D CPU Wakeup Input
5 FB1, Feedback Buck1 I A Buck 1 Feedback
6 V
IN
1 = V
BATT
I P Battery Input for Powering Internal
Circuits and LDO1-3
7 LDO_V
OUT
_1 O P LDO1 Output
8 LDO_V
OUT
_2 O P LDO2 Output
9 nRST In I D Chip Reset Input
10 LDO GND 1 G G Ground
11 LDO V
REF
Bypass O A Bypass Capacitor for Reference
12 LDO_V
OUT
_3 O P LDO3 Output
13 LDO_V
OUT
_4 O P LDO4 Output
14 V
IN
LDO_4 I P Input Power for LDO4
15 Back-Up Battery V
IN
I P Back Up Battery Input
16 LDO_V
OUT
_0 (RTC) O P LDO_RTC Output
17 nBatt_FLT O D Main Battery Fault Output
18 PGND Buck2 G G Ground
19 V
OUT
Buck2 O P Buck Switcher2 Output
20 V
IN
Buck2 I P Buck Switcher 2 Battery Input
21 SDA I/O D I
2
C Data Line
22 SCL I D I
2
C Clock Input
23 FB2, Feedback Buck2 I A Buck Switcher 2 Feedback
24 nRST Out O D Reset Output
25 LDO_V
OUT
_5 O P LDO5 Output
26 V
IN
2 (LDO 5 Only) I P Battery Input Power for LDO5
27 VDDA I P Analog Power Input
28 FB3, Feedback Buck3 I A Buck Switcher 3 Feedback
29 GPIO1/nCHG_EN I/O D General Purpose I/O #1/BUBATT
Charger EN
30 GPIO2 I/O D General Purpose I/O #2
31 V
IN
Buck3 I P Buck Switcher 3 Battery Input
32 V
OUT
Buck3 I P Buck Switcher 2 Output
33 PGND Buck3 G G Buck3 NMOS Power Ground
34 Buck 1 2 & 3 AVSS/NCHBLK G G Buck1, 2, 3 Analog Ground
35 SYNC (Buck Clock input) I D Buck Switcher External Clock Input
36 Sys_En I D Power Domain Enable
37 Pwr_En I D Power Domain Enable
38 PGND Buck1 G G Buck1 NMOS Power Ground
39 V
OUT
Buck1 O P Buck Switcher 1 Output
40 V
IN
Buck1 I P Buck Switcher 1 Battery Input
(1)
A: Analog Pin; D: Digital Pin; G: Ground Pin; I: Input Pin; I/O: Input/Output; O: Output Pin; P: Power Pin
3
SNVA235A–May 2007–Revised April 2013 AN-1621 LP3972 USB Evaluation Board Rev B
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