Datasheet

VCC_RTC
nRSTO
nBATT_FLT
SYS_EN
High-Volt_PD
nRESET_OUT
PWR_EN
Low-Volt_PD
t
5
13 MHZ_OSC
PXA27x Output
PXA27x Output
PXA27x Output
PXA27x Output
1.
2.
3,4.
5.
6.
7.
8.
9,10.
t
2
t
4
t
1
t
3
Main Batt
V
IN
BU Batt
V
IN
LP3972
www.ti.com SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
* Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the
two signals is independent of each other and can occur is either order.
Figure 30.
POWER-ON TIMING
Symbol Description Min Typ Max Unit
t1 Delay from V
CC
_RTC assertion to nRSTO de-assertion 50 mS
t2 Delay from nBATT_FLT de-assertion to nRSTI assertion 100 µS
t3 Delay from nRST de-assertion to SYS_EN assertion 10 mS
t4 Delay from SYS_EN assertion to PWR_EN assertion 125 mS
t5 Delay from PWR_EN assertion to nRSTO de-assertion 125 mS
HARDWARE RESET SEQUENCE
Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters
hardware reset state. The LP3972 holds the nRST low long enough (50 ms typ.) to allow the processor time to
initiate the reset state.
RESET SEQUENCE
1. nRSTI is asserted.
2. nRSTO is asserted and will de-asserts after a minimum of 50 mS
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (V
IN
) is
available.
4. After system power (V
IN
) is turned on, the LP3972 de-asserts nBATT_FLT.
5. The Applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies.
The Applications processor starts its countdown timer.
6. The LP3972 enables the high-voltage power supplies.
7. Countdown timer expires; the Applications processor asserts PWR_EN to enable the low-voltage power
supplies. The processor starts the countdown timer.
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