Datasheet

LP3972

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SNVS468K –SEPTEMBER 2006–REVISED MAY 2013

POWER DOMAIN ENABLES

PMU Output HW Enable SW Enable

LDO_RTC — —

LDO1 (V

_MVT) SYS_EN LDO1_EN

LDO2 SYS_EN LDO2_EN

LDO3 SYS_EN LDO3_EN

LDO4 SYS_EN LDO4_EN

LDO5 (V

_SRAM) PWR_EN S_EN

Buck1 (V

_APPS) PWR_EN A_EN

BUCK2 SYS_EN B2_EN

BUCK3 SYS_EN B3_EN

POWER DOMAINS SEQUENCING (DELAY)

By default SYS_EN must be on to have PWR_EN enable but this feature can be switched off by register bit

BP_SYS.

By default SYS_EN enables LDO1 always first and after a typical of 1 ms delay others. Also when SYS_EN is

set off the LDO1 will go off last. This function can be switched off or delay can be changed by DELAY bits via

serial interface as seen on table below.

8h’80 Bit 5:4

DELAY bits ‘00’ ‘01’ ‘10’ ‘11’

Delay, ms 0 0.5 1.0 1.5

LDO_RTC TRACKING (nIO_TRACK)

LP3972 has a tracking function (nIO_TRACK). When enabled, LDO_RTC voltage will track LDO3 voltage within

200 mV down to 2.8V when LDO3 is enabled. This function can be switched on/off by nIO_TRACK register bit

BPTR.

POWER SUPPLY ENABLE

SYS_EN and PWR_EN can be changed by programmable register bits.

WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG, SPARE AND EXT_WAKEUP)

Three input pins can be used to assert wakeup output for 10 ms for application processor notification to wakeup.

SPARE Input can be programmed through I

C compatible interface to be active low or high (SPARE bit, Default

is active low ‘1’). A reason for wakeup event can be read through I

C compatible interface also. Additionally

wakeup inputs have 30 ms de-bounce filtering. Furthermore PWR_ON have distinguishing between short and

long (∼1s) pulses (push button input). LP3972 also has an internal Thermal Shutdown early warning that

generates a wakeup to the system also. This is generated usually at 125°C.

Product Folder Links: LP3972