Datasheet

0 0 0 1 0 0 0 0
Register Address
Ack
OVER1 (8Z[10)
0 0 0 0 0 1 1 1
Data
Ack
Register Data (00000111)
0 0 1 0 1 0 0 1
Register Address
Ack
SDTV1 (8Z[29)
0 0 0 1 1 0 1 1
Data
Ack
Register Data (00011011)
0 0 1 0 0 0 1 1
Register Address
Ack
ADTV1 (8Z[23)
0 0 0 1 1 0 1 1
Data
Ack
Register Data (00011011)
0 1 1 0 1 0 0 0
Device ID Ack
Stop
Start
W
LP3972
www.ti.com SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
MARVELL PXA INTERNAL 2 REVISION REGISTER (II2RR) 8H’8F
Bit 7 6 5 4 3 2 1 0
Designation II2RR
Reset Value 0 0 0 0 0 0 0 0
MARVELL PXA INTERNAL 2 REVISION REGISTER (II2RR) 8H’8F DEFINITIONS
Bit Access Name Description
7:0 R II2RR Intel internal usage register for revision information.
REGISTER PROGRAMMING EXAMPLES
Example 1) Start of Day Sequence
PMIC Register PMIC Register
Register Data Description
Address Name
8h’23 ADTVI 00011011 Sets the SOD V
CC
_APPS voltage
8h’29 SDTV1 00011011 Sets the SOD V
CC
_SRAM voltage
8h’10 OVER1 00000111 Enables V
CC
_SRAM and V
CC
_APPS to their programmed values.
SODl Multi-byte random register transfer is outlined below:
Figure 26.
Device Address,
Register A Address, Ach,
Register A Data, Ach
Register M Address, Ach,
Register M Data, Ach
Register X Address, Ach,
Register X Data, Ach
Register Z Address, Ach,
Register Z Data, Ach, Stop
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