Datasheet

LP3972
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
Bit Access Name Description
1 R WUPT TEST_JIG Pin Wake Up Status
0 = No wake up event
1 = Wake up event
0 R WUPS SPARE Pin Wake Up Status
0 = No wake up event
1 = Wake up event
BACKUP BATTERY CHARGER CONTROL REGISTER (BCCR)
This register specifies the status of the main battery supply. NBUB bit
Backup Battery Charger Control Register (BCCR) 8h’89
Bit 7
(1)
6 5
(1)
4
(1)
3
(1)
2 1 0
Designation NBUB CNBFL nBFLT BUCEN IBUC
Reset Value 0 0 0 1 0 0 0 1
(1) One time factory programmable EPROM registers for default values
Backup Battery Charger Control Register (BCCR) 8h’89 Definitions
Bit Access Name Description
7 R/W NBUB No back-up battery default setting. Logic will not allow switch over to back-up
battery.
0 = Back up Battery Enabled, Default
1 = Back up Battery Disabled
6 R/W CNBFL Control for nBATT_FLT output signal
0 = nBATT_FLT Enabled
1 = nBATT_FLT Disabled
nBATT_FLT monitors the battery voltage and can be set to the Assert voltages
listed below.
Data Code Asserted De-Asserted
3h’01 2.6 2.8
5:3 R/W BFLT
3h’02 2.8 3.0 (Default)
3h’03 3.0 3.2
3h’04 3.2 3.4
3h’05 3.4 3.6
2 R/W BUCEN Enables backup battery charger
0 = Back up Battery Charger Disabled
1 = Back up Battery Charger Enabled
Charger current setting for back-up battery
Data Code BU Charger I (µA)
2h’00 260
1:0 R/W IBUC
2h’01 190 (Default)
2h’02 325
2h’03 390
MARVELL PXA INTERNAL 1 REVISION REGISTER (II1RR) 8H’8E
Bit 7 6 5 4 3 2 1 0
Designation II1RR
Reset Value 0 0 0 0 0 0 0 0
MARVELL PXA INTERNAL 1 REVISION REGISTER (II1RR) 8H’8E DEFINITIONS
Bit Access Name Description
7:0 R II1RR Intel internal usage register for revision information.
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