Datasheet

Cchg_det
4.7 PF
VIN
DC SOURCE
4.5 ± 5.5V
Li-ion/polymer cell
+
OSC
PGND3
Logic Control
and registers
I2C
PGND1
VoutLDO2
Cldo1
1.0 PF
LDO2
SW2
VFB2
BUCK3
SW3
vref
PGND2
PWR_ON
Cvrefh
10 nF
VREF
Cvdd
4.7 PF
Vin_BUCK1
Vin_BUCK2
SYNC
VDDA
BUCK1
BUCK2
Lsw2 2.2 PH
SW1
VFB1
LDO3
LDO4
LDO5
RTC
SRAM
PLL
CODEC
SYS_EN
PWR_EN
RESET
Clock
divider
VoutLDO3
VoutLDO4
VoutLDO5
EOC
nTEST_JIG
SPARE
EXT_WAKEUP
nRSTI
GND1
VinLDO4
VinBUBATT
VoutLDO_RTC
nBATT_FLT
nRSTO
VinLDO5
GPIO1/nCHG_EN
GPIO2
BGND1,2,3
-+
UART
CPU
CORE
Wake up
LDORTC
VFB3
BIAS
Thermal
Shutdown
Power On
Reset
Lsw1 2.2 PH
Lsw3 2.2 PH
Internal HW reset for
test purposes
VoutLDO_RTC
SYS_EN
VIN
Vout Switch
VIN
6
27
35
40
Vin_BUCK3
20
31
AP_IO
USB
BG
MVT
37
39
5
19
28
36
23
32
12
13
25
16
15
9
8
1
29
11
2
3
30
38
18
33
34
10
VinLDO4
VinLDO5
1426
I2C_SDA
I2C_SCL
VBUCK2
22
21
24
4
17
COMP
LDO1
VoutLDO1
7
PWR_EN
Vout
Switch
See notes
3.3V
See notes
VDDA
10 PF
CldoRTC
1.0 PF
Cldo5
0.47 PF
Power
ON-OFF
Logic
10k
10k
APPLICATION
PROCESSOR
LP3972 PMIC
Cldo4
0.47 PF
Cldo3
0.47 PF
Cldo2
0.47 PF
10 PF
10 PF
LP3972
www.ti.com SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
• The I
2
C lines are pulled up via a I/O source
• V
IN
LDOs 4, 5 can either be powered from main battery source, or by a buck regulator or V
IN
.
Figure 2. Application Circuit
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