Datasheet

LP3972
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
LDO5 (V
CC
_SRAM) TARGET VOLTAGE 2 REGISTER
LDO5 (V
CC
_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A
Bit 7 6 5 4 3 2 1 0
Designation Reserved LDO 5 Output Voltage (L5OV)
Reset Value 0 0 0 0 1 0 1 1
LDO5 (V
CC
_SRAM) Target Voltage 2 Register (SDTV2) 8h’2A Definitions
Bit Access Name Description
7:5 — — Reserved
4:0 R/W B1OV Data Code Output Voltage Data Code Output Voltage
5h’0 — 5h’10 1.125
5h’1 — 5h’11 1.150
5h’2 — 5h’12 1.175
5h’3 — 5h’13 1.200
5h’4 — 5h’14 1.225
5h’5 0.850 5h’15 1.250
5h’6 0.875 5h’16 1.275
5h’7 0.900 5h’17 1.300
5h’8 0.925 5h’18 1.325
5h’9 0.950 5h’19 1.350
5h’A 0.975 5h’1A 1.375
5h’B 1.000 5h’1B 1.400
5h’C 1.025 5h’1C 1.425
5h’D 1.050 5h’1D 1.450
5h’E 1.075 5h’1E 1.475
5h’F 1.100 5h’1F 1.500
V
CC
_MVT is low tolerance regulated power supply for the application processor ring oscillator and logic for
communicating to the LP3972. V
CC
_MVT is enabled when SYS_EN is asserted and disabled when SYS_EN is
deasserted.
LDO1 (V
CC
_MVT) TARGET VOLTAGE 1 REGISTER (MDTV1)
LDO1 (V
CC
_MVT) Target Voltage 1 Register (MDTV1) 8h’32
Bit 7 6 5 4
(1)
3
(1)
2
(1)
1
(1)
0
(1)
Designation Reserved Output Voltage (OV)
Reset Value 0 0 0 0 0 1 0 0
(1) One-time factory programmable EPROM registers for default values
LDO1 (V
CC
_MVT) Target Voltage 1 Register (MDTV1) 8h’32 Definitions
Bit Access Name Description
7:5 — — Reserved
4:0 R/W L1OV Data Code Output Voltage Notes:
5h’0 1.700
5h’1 1.725
5h’2 1.750
5h’3 1.775
5h’4 1.800
5h’5 1.825
5h’6 1.850
5h’7 1.875
5h’8 1.900
5h’9 1.925
5h’A 1.950
5h’B 1.975
5h’C 2.000
5h’D-5h’F Reserved
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