Datasheet

LP3972
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
LP3972 CONTROL REGISTER
Register Address Register Name Read/Write Register Description
8h’07 SCR R/W System Control Register
8h’10 OVER1 R/W Output Voltage Enable Register 1
8h’11 OVSR1 R Output Voltage Status Register 1
8h’12 OVER2 R/W Output Voltage Enable Register 2
8h’13 OVSR2 R Output Voltage Status Register 2
8h’20 V
CC
1 R/W Voltage Change Control Register
1
8h’23 ADTV1 R/W Buck1 Target Voltage 1 Register
8h’24 ADTV2 R/W Buck1 DVM Target Voltage 2
Register
8h’25 AVRC R/W V
CC
_APPS Voltage Ramp
Control
8h’26 CDTC1 W Dummy Register
8h’27 CDTC2 W Dummy Register
8h’29 SDTV1 R/W LDO5 Target Voltage 1
8h’2A SDTV2 R/W LDO5 Target Voltage 2
8h’32 MDTV1 R/W LDO1 Target Voltage 1 Register
8h’33 MDTV2 R/W LDO1 Voltage 2 Register
8h’39 L2VCR R/W LDO2 Voltage Control Registers
8h’3A L34VCR R/W LDO3 & LDO4 Voltage Control
Registers
8h’80 SCR1 R/W System Control Register 1
8h’81 SCR2 R/W System Control Register 2
8h’82 OEN3 R/W Output Voltage Enable Register 3
8h’83 OSR3 R/W Output Voltage Status Register 3
8h’84 LOER4 R/W Output Voltage Enable Register 3
8h’85 B2TV R/W V
CC
_Buck2 Target Voltage
8h’86 B3TV R/W V
CC
_Buck3 Target Voltage
8h’87 B32RC R/W Buck 3:2 Voltage Ramp Control
8h’88 ISRA R Interrupt Status Register A
8h’89 BCCR R/W Backup Battery Charger Control
Register
8h’8E II1RR R Internal 1 Revision Register
8h’8F II2RR R Internal 2 Revision Register
SERIAL INTERFACE REGISTER SELECTION CODES (Bold face voltages are default values)
System Control Status Register
Register is an 8-bit register which specifies the control bits for the PMIC clocks. This register works in
conjunction with the SYNC pin where an external clock PLL buffer operating at 13 MHz is synchronized with the
oscillators of the buck converters.
System Control Register (SCR) 8h’07
Bit 7 6 5 4 3 2 1 0
Designation Reserved CLK_SCL
Reset Value 0 0 0 0 0 0 0 0
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