Datasheet

msb Register Add lsbmsb Chip Address lsbstart ackw msb DATA1 lsback ack ack ack stop
ack from slave ack from slave ack from slave ack from slave ack from slave
Register 0x24 Data (reg_0x24)
msb DATA2 lsb msb DATA3 lsb
Data (reg_0x25) Data (reg_0x26)
msb Register Add lsbmsb Chip Address lsbstart ackw msb DATA lsback msb Register Add lsback msb DATA lsback ack stop
ack from slave ack from slave ack from slave ack from slave ack from slave
Register 0x24 Register 0x2A
LP3972
www.ti.com SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
MULTI-BYTE I
2
C COMMAND SEQUENCE
To correctly function with the Monahan’s Power Management I
2
C the LP3972’s I
2
C serial interface shall support
Random register Multi-byte command sequencing: During a multi-byte write the Master sends the Start command
followed by the Device address, which is sent only once, followed by the 8 Bit register address, then 8 bits of
data. The I
2
C slave must then accept the next random register address followed by 8 bits of data and continue
this process until the master sends a valid stop condition.
A Typical Multi-byte random register transfer is outlined below:
Device Address,
Register A Address, Ach,
Register A Data, Ach
Register M Address, Ach,
Register M Data, Ach
Register X Address, Ach,
Register X Data, Ach
Register Z Address, Ach,
Register Z Data, Ach, Stop
Note: The PMIC is not required to see the I
2
C device address for each transaction. A, M, X, and Z are Random
numbers.
Figure 24.
INCREMENTAL REGISTER I
2
C COMMAND SEQUENCE
The LP3972 supports address increment (burst mode). When you have defined register address n data bytes
can be sent and register address is incremented after each data byte has been sent. Address incrimination may
be required for non XScale applications. User can define whether multi-byte (default) to random address or
address incrimination will be used.
Figure 25.
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