Datasheet

DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START
condition
S
acknowledge
1 8 9
I
2
C - bus.
clock pulse for
acknowledgement
V
CC
_APPS
9ROWDJHµµ$¶¶
9ROWDJHµµ%¶¶
5 Ps TYP
start msb Chip Address lsb
SCL
w msb Register Add lsb rs r msb DATA lsb stop
SDA
start
Id = 34h w ack addr = 00h ack rs
r ack $GGUHVVK¶00 data ack stop
msb Chip Address lsb
Id = 34h
ackackackack
start msb Chip Address lsb w ack Msb Register Add lsb ack msb DATA lsb ack stop
SCL
SDA
start Id = 34h w ack addr = 02h ack ackDGGUHVVK¶02 data stop
LP3972
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
Write Cycle
Figure 21. Write cycle
Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.
w = write (SDA = "0")
r = read (SDA = "1")
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 34h (Chip Address)
Figure 22. Read Cycle
Figure 23. I
2
C DVM Timing for V
CC
_APPS (Buck1)
20 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3972