Datasheet
V
OUT
TIME (4 Ps/DIV)
200 mA/DIV
I
L
V
SW
2V/DIV
20 mV/DIV
AC Coupled
V
IN
= 3.6V
V
OUT
= 1.5V
I
OUT
= 20 mA
V
OUT
TIME (200 ns/DIV)
200 mA/DIV
I
L
V
SW
2V/DIV
10 mV/DIV
AC Coupled
V
IN
= 3.6V
V
OUT
= 1.5V
I
OUT
= 400 mA
LP3972
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013
www.ti.com
Figure 15. Typical PWM Operation
Internal Synchronous Rectification
While in PWM mode, the converters uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
Current Limiting
A current limit feature allows the converters to protect itself and external components during overload conditions.
PWM mode implements current limiting using an internal comparator that trips at 2.0 A (typ). If the output is
shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration
until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby
preventing runaway.
PFM OPERATION
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
1. The inductor current becomes discontinuous.
2. The peak PMOS switch current drops below the I
MODE
level, (Typically I
MODE
< 30 mA + V
IN
/42Ω).
Figure 16. Typical PFM Operation
16 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3972