Datasheet

LP3972
SNVS468K –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
Logic Inputs and Outputs DC Operating Conditions
(1)
Logic Inputs (SYS_EN, PWR_EN, SYNC, nRSTI, PWR_ON, nTEST_JIG, SPARE and GPI's)
Symbol Parameter Test Conditions Min Max Unit
V
IL
Low Level Input Voltage 0.5 V
V
IH
High Level Input Voltage V
RTC
− 0.5V V
I
LEAK
Input Leakage Current −1 +1 µA
(1) All voltages are with respect to the potential at the GND pin.
Logic Outputs (nRSTO, EXT_WAKEUP and GPO's)
Symbol Parameter Test Conditions Min Max Unit
V
OL
Output Low Level Load = +0.2 mA = I
OL
Max 0.5 V
V
OH
Output High Level Load = −0.1 mA = I
OL
Max V
RTC
− 0.5V V
I
LEAK
Output Leakage Current V
ON
= V
IN
+5 µA
Logic Output (nBATT_FLT)
Symbol Parameter Test Conditions Min Typ Max Unit
nBATT_FLT Threshold Voltage Programmable via Serial Interface 2.4 2.8 3.4 V
Default = 2.8V
V
OL
Output Low Level Load = +0.4 mA = I
OL
Max 0.5 V
V
OH
Output High Level Load = −0.2 mA = I
OH
Max V
RTC
− 0.5V V
I
LEAK
Input Leakage Current +5 µA
I
2
C Compatible Serial Interface Electrical Specifications (SDA and SCL)
Unless otherwise noted, V
IN
= 3.6V. Typical values and limits appearing in normal type apply for T
J
= 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C
(1)(2)(3)
Symbol Parameter Test Conditions Min Typ Max Unit
V
IL
Low Level Input Voltage See
(4)
−0.5 0.3 V
RTC
V
V
IH
High Level Input Voltage See
(4)
0.7 V
RTC
V
RTC
V
OL
Low Level Output Voltage See
(4)
0 0.2 V
TRC
I
OL
Low Level Output Current V
OL
= 0.4V
(4)
3.0 mA
F
CLK
Clock Frequency See
(4)
400 kHz
t
BF
Bus-Free Time Between Start and Stop See
(4)
1.3 µs
t
HOLD
Hold Time Repeated Start Condition See
(4)
0.6 µs
t
CLKLP
CLK Low Period See
(4)
1.3 µs
t
CLKHP
CLK High Period See
(4)
0.6 µs
t
SU
Set Up Time Repeated Start Condition See
(4)
0.6 µs
t
DATAHLD
Data Hold Time See
(4)
0 µs
t
CLKSU
Data Set Up Time See
(4)
100 ns
T
SU
Set Up Time for Start Condition See
(4)
0.6 µs
T
TRANS
Maximum pulse width of spikes that must be See
(4)
50 ns
suppressed by the input filter of both DATA and
CLK signals
(1) All voltages are with respect to the potential at the GND pin.
(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
production tested, ensured through statistical analysis or ensured by design. All limits at temperature extremes are ensured via
correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level
(AOQL).
(3) The I
2
C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20 kΩ
range.
(4) This electrical specification is ensured by design.
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