Datasheet

LP3962, LP3965
SNVS066H –MAY 2000–REVISED APRIL 2013 www.ti.com
Pin Descriptions for SOT-223-5 Package
LP3962 LP3965
Pin #
Name Function Name Function
1 SD Shutdown SD Shutdown
2 V
IN
Input Supply V
IN
Input Supply
3 V
OUT
Output Voltage V
OUT
Output Voltage
4 ERROR ERROR Flag SENSE/ADJ Remote Sense Pin or Output
Adjust Pin
5 GND Ground GND Ground
Pin Descriptions for TO-220-5 and SFM/TO-263-5 Packages
LP3962 LP3965
Pin #
Name Function Name Function
1 SD Shutdown SD Shutdown
2 V
IN
Input Supply V
IN
Input Supply
3 GND Ground GND Ground
4 V
OUT
Output Voltage V
OUT
Output Voltage
5 ERROR ERROR Flag SENSE/ADJ Remote Sense Pin or Output
Adjust Pin
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 5 sec.) 260°C
ESD Rating
(3)
2 kV
Power Dissipation
(4)
Internally Limited
Input Supply Voltage (Survival) −0.3V to +7.5V
Shutdown Input Voltage (Survival) −0.3V to V
IN
+0.3V
Output Voltage (Survival),
(5)
,
(6)
−0.3V to +7.5V
I
OUT
(Survival) Short Circuit Protected
Maximum Voltage for ERROR Pin V
IN
+0.3V
Maximum Voltage for SENSE Pin V
OUT
+0.3V
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions,
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
(4) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be
derated at θ
jA
= 50°C/W (with 0.5in
2
, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the SFM/TO-263
surface-mount package must be derated at θ
jA
= 60°C/W (with 0.5in
2
, 1oz. copper area), junction-to-ambient. The devices in SOT-223
package must be derated at θ
jA
= 90°C/W (with 0.5in
2
, 1oz. copper area), junction-to-ambient.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to
ground.
(6) The output PMOS structure contains a diode between the V
IN
and V
OUT
terminals. This diode is normally reverse biased. This diode will
get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can
typically withstand 200mA of DC current and 1Amp of peak current.
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