Datasheet
LP3907
24 Pin LLP
ENLDO2
LDO2
VINLDO2
VINLDO12
GND
GND
GND
C5
C2
1 PF-16V-X7R-S
1 PF-16V-X7R-S
0.47 PF-25V-X7R-S
C1
VINLDO12
1
VINLDO2
24
LDO2
23
ENLDO2 ENLDO1
21
LDO1
20
VINLDO1
19
GND_L
18
SCL
17
SDA
16
GND_SW2
15
SW2
14
VIN2
13
SMB
JACK
GND
GND
7
ENSW1
8
FB1
9
GND_C
10
AVDD
11
FB2
12
ENSW2
VIN1
6
SW1
5
EN_T
2
NPOR
3
GND_SW1
4
NPOR
EN_T
VDD_M
GND_SW1
GND
100k
R15
VIN1
GND
SMB
JACK
L3
2.2 PH
S1
BUCK1
21
VBUCK1
C3
10 PF-16V-X7R-S
GND
C4
10 PF-16V-X7R-S
ENSW1
GND
Generic
R12
GND
GND_M GND_M GND_M
Generic
C11
GND
VBUCK1
Generic
R14
C13
Generic
R13
Generic
C12
GND
C14
10 PF-16V-X7R-S
Generic
Generic
R11
C10
Generic
VBUCK2
ENSW2
VIN2
GND
C9
10 PF-16V-X7R-S
VDD_M
R1
22K-S
VDD_M
R2
22K-S
GND
GND_SW2
GND_LF
BUCK2
GND
VDD_MVDD_M
JP1
VIN1
S2
L2
2.2 PH
21
C8
10 PF-16V-X7R-S
VBUCK2
ENLDO1
LDO1
VINLDO1
C6
C7
1 PF-16V-X7R-S
0.47 PF-25V-X7R-S
VIN BUCK1
TO MAIN VDD
VIN BUCK2
TO MAIN VDD
BUCK CORE VDD
TO MAIN VDD
LDO1 FET VDD
TO MAIN VDD
LDO1/2 CORE VDD
TO MAIN VDD
LDO2 FET VDD
TO MAIN VDD
VDD_MVDD_M
JP2
VIN2
VDD_M
JP3
AVDD
VDD_M
JP4
VINLDO1
VDD_M
JP5
VINLDO12
VDD_M
JP6
VINLDO2
VDD_M
JP12
ENSW2
VDD_M
JP11
ENSW1
VDD_M
JP10
ENLDO2
VDD_M
JP9
ENLDO1
JP8
LDO1
GND
JP7
LDO2
GND
NOTE: VDD_M CONNECTS THE MAIN
VDD PLANE TO VARIOUS BLOCKS.
TO ISOLATE ANY BLOCK FROM VDD
SIMPLY DISCONNECT THE
CORRESPONDING JUMPER.
22
Using the Evaluation Hardware
www.ti.com
Table 1. Jumper Settings (continued)
*ADC These jumpers connect outputs of various Needs to be jumpered to measure the voltages of different
regulators to the ADCs of the USB. regulators from the GUI.
Figure 14. LP3907 Evaluation Board Schematic
12
AN-1619 Evaluation Kit for LP3907 — Programmable Power Management SNVA233A–September 2007–Revised April 2013
Unit with 1
2
C Compatible Interface
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