Datasheet

LP3906
SNVS456M –AUGUST 2006–REVISED MAY 2013 www.ti.com
LOW DROP OUT REGULATORS, LDO1 AND LDO2
Unless otherwise noted, V
IN
= 3.6, C
IN
= 1.0 µF, C
OUT
= 0.47 µF. Typical values and limits appearing in normal type apply for
T
J
= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to
+125°C.
(1)(2) (3)(4)(5)(6) (7)
Parameter Test Conditions Min Typ Max Units
V
IN
Operational Voltage Range VINLDO1 and VINLDO2 PMOS
1.74 5.5 V
pins
(8)
V
OUT
Accuracy Output Voltage Accuracy (Default V
OUT
) Load current = 1 mA −3 3 %
ΔV
OUT
Line Regulation V
IN
= (V
OUT
+ 0.3V) to 5.0V,
0.15 %/V
(7)
, Load Current = 1 mA
Load Regulation V
IN
= 3.6V,
0.011 %/mA
Load Current = 1 mA to I
MAX
I
SC
Short Circuit Current Limit LDO1-2, V
OUT
= 0V 500 mA
V
IN
– V
OUT
Dropout Voltage Load Current = 50 mA
(5)
25 200 mV
PSRR Power Supply Ripple Rejection F = 10 kHz, Load Current = I
MAX
45 dB
θn Supply Output Noise 10 Hz < F < 100 KHz 80 µVrms
I
Q
(6) (9)
Quiescent Current “On” I
OUT
= 0 mA 40 µA
Quiescent Current “On” I
OUT
= I
MAX
60 µA
Quiescent Current “Off” EN is de-asserted
(10)
0.03 µA
T
ON
Turn On Time Start up from shut-down 300 µs
C
OUT
Output Capacitor Capacitance for stability 0°C ≤ T
J
0.33 0.47 µF
≤ 125°C
−40°C ≤ T
J
≤ 125°C 0.68 1.0 µF
ESR 5 500 mΩ
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most
likely norm.
(3) C
IN
, C
OUT
: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(4) The device maintains a stable, regulated output voltage without a load.
(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V
OUT
.
(7) V
IN
minimum for line regulation values is 1.8V.
(8) Pins 13, 19 can operate from Vin min of 1.74 to a Vin max of 5.5V this rating is only for the series pass pmos power fet. It allows the
system design to use a lower voltage rating if the input voltage comes from a buck output.
(9) The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled
via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two
values can be used by the system designer when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to
disable each block of the IC please contact the factory applications for IQ details.
(10) The Iq exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2µA
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