Datasheet

OSC
Logic
Control
and
registers
I
2
C
GND_SW1
SW
2
FB
2
vref
GND_
SW2
Cvdd
4
. 7
P
F
VIN
1
VIN
2
SYNC
BUCK
1
BUCK
2
Lsw
2 2
.
2
P H
SW
1
FB
1
LDO
2
RESET
Clock
divider
LDO
2
GND_C
BIAS
Thermal
Shutdown
Power On
Reset
Lsw
1 2
. 2
P
H
VINLDO
1
20
19
23
7
VINLDO
1
1
13
6
11
2
21
18
5
4
17
AVDD
SDA
SCL
VBUCK
2
LDO
1
LDO
1
14
Cldo
1
0
. 47
P
F
VinLDO
12
Csw2
10
P F
Csw
1
10
P
F
Cldo
2
0
. 47
P F
Power
ON
- OFF
Logic
FPGA
LP
3906
PMIC
Flash
VBUCK
1
3
EN
_
T
10
9
8
12
ENLDO
1
15
ENLDO
2
16
GND_
L
VINLDO2
VINLDO
12
ENSW
1
ENSW
2
24
22
CPU
CORE
I
/ O
1
. 8
V
1 . 2
V
3 .
3 V
3 .
3 V
VBUCK2
3
.3V
VINLDO
2
AVDD
AVDD
10
P F
10
P
F
1
P
F
1
P
F
1
P
F
1 P
F
DC SOURCE
4 . 5
±
5
. 5
V
Li
- ion
/
polymer cell
3 .
6 V -
4 .
2 V
+
*
*
Programmable
Application
Processor
LP3906
www.ti.com SNVS456M –AUGUST 2006–REVISED MAY 2013
Figure 2. Typical Application Circuit
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