Datasheet

EN_T
Vout Buck1
Vout Buck2
Vout LDO1
Vout LDO2
t
1
t
2
t
3
t
4
LP3906
www.ti.com SNVS456M –AUGUST 2006–REVISED MAY 2013
NOTE
LP3906 The default Power on delays can be reprogrammed at final test or I
2
C to 1, 1.5, 2,
3, 6, or 11 ms.
LP3906 Default Power-Off Sequence
Symbol Description Min Typ Max Units
t
1
Programmable Delay from EN_T deassertion to V
CC
_Buck1 Off 1.5 ms
t
2
Programmable Delay from EN_T deassertion to V
CC
_Buck2 Off 2 ms
t
3
Programmable Delay from EN_T deassertion to V
CC
_LDO1 Off 3 ms
t
4
Programmable Delay from EN_T deassertion to V
CC
_LDO2 Off 6 ms
NOTE
LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or
10 ms. Default setting is the same as the on sequence.
Power-On-Reset
The LP3906 is equipped with an internal Power-On-Reset (“POR”) circuit that will reset the logic when VDD <
V
POR
. This ensures that the logic is properly initialized when VDD rises above the minimum operating voltage of
the Logic and the internal oscillator that clocks the Sequential Logic in the Control section.
I
2
C Compatible Serial Interface
I
2
C SIGNALS
The LP3906 features an I
2
C compatible serial interface, using two dedicated pins: SCL and SDA for I
2
C clock
and data respectively. Both signals need a pull-up resistor according to the I
2
C specification. The LP3906
interface is an I
2
C slave that is clocked by the incoming SCL clock.
Signal timing specifications are according to the I
2
C bus specification. The maximum bit rate is 400 kbit/s. See
I
2
C specification from Philips for further details.
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