Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - power management - special purpose WQFN 24 (4x5)

VINLDO12

SYNC

VIN1

SW1

FB1

GND_SW1

VIN2

SW2

2.2 PH

10 PF

1 PF

10 PF

FB2

GND_SW2

AVDD

10 PF

1 PF

0.47 PF

1 PF

0.47 PF

GND_C

GND_L

SCL

SDA

LDO2

LDO1

VINLDO2

VINLDO1

ENSW2

ENSW1

ENLDO2

ENLDO1

EN_T

LP3906

DAP

LP3906

www.ti.com

SNVS456M –AUGUST 2006–REVISED MAY 2013

Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible

Interface

Check for Samples: LP3906

FEATURES

KEY SPECIFICATIONS

• Compatible with Advanced Applications

• DC/DC Converter (Buck)

Processors and FPGAs

– 1.5A Output Current

• 2 LDOs for Powering Internal Processor

– Programmable V

OUT

from:

Functions and I/Os

– Buck1 : 0.8V–2.0V

• High Speed Serial Interface for Independent

– Buck2 : 1.0V–3.5V

Control of Device Functions and Settings

– Up to 96% Efficiency

• Precision Internal Reference

– 2 MHz PWM Switching Frequency

• Thermal Overload Protection

– ±3% Output Voltage Accuracy

• Current Overload Protection

– Automatic Soft Start

• 24-lead 5 × 4 × 0.8 mm WQFN Package

• Linear Regulators (LDO)

• Software Programmable Regulators

– Programmable V

OUT

of 1.0V–3.5V

– ±3% Output Voltage Accuracy

APPLICATIONS

– 300 mA Output Currents

• FPGA, DSP Core Power

– 25 mW (Typ) Dropout

• Applications Processors

• Peripheral I/O Power

DESCRIPTION

The LP3906 is a multi-function, programmable Power

Management Unit, optimized for low power FPGAs,

Microprocessors and DSPs.

Typical Application Circuits

Figure 1. Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

PAGE 1
LP3906 www.ti.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com For information about how schottky diodes can reduce noise in high load, high Vin applications, see Buck Output Ripple Management. DESCRIPTION (CONTINUED) This device integrates two highly efficient 1.5A Step-Down DC/DC converters with dynamic voltage management (DVM), two 300mA Linear Regulators and a 400kHz I2C compatible interface to allow a host controller access to the internal control registers of the LP3906.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 DC SOURCE 4.5 ± 5.5V + Li-ion/polymer cell 3.6V - 4.2V FPGA 12 1 PF 13 VIN1 10 PF VIN2 19 1 PF VINLDO1 20 1 PF AVDD 1 PF VINLDO2 VINLDO12 LP3906 PMIC Cvdd 4.7 PF 1 10 PF SYNC 23 7 Clock divider OSC 6 BUCK1 AVDD 10 EN_T Lsw1 2.2 PH 1.2V VBUCK1 SW1 *FB1 Csw1 10 PF CPU CORE 11 15 ENLDO1 16 Power ON-OFF Logic ENLDO2 22 BUCK2 AVDD ENSW1 Lsw2 2.2 PH 3.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com Connection Diagram 19 18 17 16 15 14 13 20 12 21 11 22 10 23 9 24 8 1 2 3 4 5 6 7 Figure 3. 24-Lead WQFN Package (Top View) See Package Number NHZ0024B Table 1. Default Voltage Options (1) (2) Part Number Package Marking Buck1 Buck2 LDO1 LDO2 LP3906SQ-DJXI/NOPB 06-DJXI 0.9V 1.8V 3.3V 1.8V LP3906SQ-FXPI/NOPB 06-FXPI 1.0V 3.3V 2.5V 1.8V LP3906SQ-JXXI/NOPB 06-JXXI 1.2V 3.3V 3.3V 1.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 Pin Descriptions (1) (1) Pin Name Pin No.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) (3) −0.3V to +6V VIN, SDA, SCL GND to GND SLUG ±0.3V Power Dissipation (PD_MAX) (TA=85°C, TMAX=125°C, ) (4) 1.43 W Junction Temperature (TJ-MAX) 150°C −65°C to +150°C Storage Temperature Range Maximum Lead Temperature (Soldering) ESD Ratings Human Body Model (1) (2) (3) (4) (5) 6 260°C (5) 2 kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 OPERATING RATINGS (1) (2) (3) Bucks VIN 2.7V to 5.5V VEN 0 to (VIN + 0.3V) −40°C to +125°C Junction Temperature (TJ) Range Ambient Temperature (TA) Range Thermal Properties (5) (6) (4) −40°C to +85°C (4) Junction-to-Ambient Thermal Resistance (θJA)NHZ0024B (1) (2) (3) (4) (5) (6) 28°C/W Absolute Maximum Ratings indicate limits beyond which damage to the component may occur.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com LOW DROP OUT REGULATORS, LDO1 AND LDO2 Unless otherwise noted, VIN = 3.6, CIN = 1.0 µF, COUT = 0.47 µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (1) (2) (3) (4) (5) (6) (7) Parameter Test Conditions Min Typ Max Units 1.74 5.5 V −3 3 % 0.15 %/V 0.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 BUCK CONVERTERS SW1, SW2 Unless otherwise noted, VIN = 3.6, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (1) (2) (3) (4) (5) Parameter VOUT Test Conditions Min Typ −3 Max Units Output Voltage Accuracy Default VOUT Line Regulation 2.7< VIN < 5.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS — LDO TA = 25°C unless otherwise noted Output Voltage Change vs Temperature (LDO2) Vin = 4.3V, Vout = 1.8V, 100 mA load 2.00 2.00 1.50 1.50 1.00 1.00 VOUT CHANGE (%) VOUT CHANGE (%) Output Voltage Change vs Temperature (LDO1) Vin = 4.3V, Vout = 3.3V, 100 mA load 0.50 0.00 -0.50 0.50 0.00 -0.50 -1.00 -1.00 -1.50 -1.50 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100 -2.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS — LDO (continued) TA = 25°C unless otherwise noted Enable Start-up time (LDO1) ) 0-3.6 Vin, 3.3 Vout, 1mA load Enable Start-up time (LDO2) 0 – 3.6 Vin, 1.8 Vout, 1 mA load Figure 10. Figure 11.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS — BUCK TA = 25°C unless otherwise noted Output Voltage vs. Supply Voltage (Vout = 1.0 V) Shutdown Current vs. Temp 0.15 0.12 1.040 1.035 1.030 1.025 1.020 1.015 1.010 1.005 1.000 0.995 0.990 OUTPUT VOLTAGE (V) SHUTDOWN CURRENT (éA) IOUT = 20 mA IOUT = 750 mA VIN = 5.5V 0.09 VIN = 3.6V 0.06 VIN = 2.7V IOUT = 1.5A 0.03 0.00 -40 -20 0 20 40 60 80 2.5 3.0 TEMPERATURE (°C) 4.5 5.0 5.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued) TA = 25°C unless otherwise noted Buck 1 Efficiency vs Output Current (PFM to PWM mode, Vout =1.2V, L= 2.2µH) Buck 1 Efficiency vs Output Current (PFM to PWM mode, Vout =2.0V, L= 2.2µH) 100 100 VIN = 2.8V 80 EFFICIENCY (%) EFFICIENCY (%) VIN = 2.8V 90 90 VIN = 5.5V 70 VIN = 3.6V 60 80 VIN = 5.5V 70 VIN = 3.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued) TA = 25°C unless otherwise noted 14 Load Transient Response Vout = 1.2 (PWM Mode) Mode Change by Load Transient Vout = 1.2V (PWM to PFM) Figure 24. Figure 25. Line Transient Response Vin = 3 – 3.6 V, Vout = 1.2 V, 250 mA load Line Transient Response Vin = 3 – 3.6 V, Vout = 3.3 V, 250 mA load Figure 26. Figure 27. Start up into PWM Mode Vout = 1.8 V, 1.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued) TA = 25°C unless otherwise noted Start up into PFM Mode Vout = 1.8 V, 30 mA load Start up into PFM Mode Vout = 3.3 V, 30 mA load Figure 30. Figure 31.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com HIGH VIN-HIGH LOAD OPERATION Additional information is provided when the IC is operated at extremes of Vin and regulator loads. These are described in terms of the Junction Temperature and Buck Output Ripple Management. Junction Temperature The maximum junction temperature TJ-MAX-OP of 125ºC of the IC package.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 5.5 VIN (V) 5.0 4.5 4.0 3.5 3.0 0 0.5 1.0 1.5 LOAD CURRENT (A) Figure 32. LP3906 Buck Converter VIN vs ILOAD Operating Ranges Thermal Performance of the WQFN Package The LP3906 is a monolithic device with integrated power FETs. For that reason, it is important to pay special attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize power dissipation of the WQFN package.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com Table 2. SUPPLY SPECIFICATION Output Supply Load LDO1 LDO2 VOUT Range(V) Resolution (mV) IMAX Maximum Output Current (mA) analog 1.0 to 3.5 100 300 analog 1.0 to 3.5 100 300 SW1 digital 0.8 to 2.0 50 1500 SW2 digital 1.0 to 3.5 100 1500 LINEAR LOW DROP-OUT REGULATORS (LDOS) LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload protection. CIRCUIT OPERATION DESCRIPTION A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 SHUTDOWN MODE During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended to disable the converter during the system power up and under voltage conditions when the supply is less than 2.8V.
PAGE 22
LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com NOTE LP3906 The default Power on delays can be reprogrammed at final test or by using I2C registers to 1, 1.5, 2, 3, 6, or 11 ms. The regulators can also be programmed through I2C to turn on and off. By default, the I2C enables for the regulators are ON. The regulators are on following the pattern below: Regulators on = (I2C enable) AND (External pin enable OR EN_T high).
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 NOTE LP3906 The default Power on delays can be reprogrammed at final test or I2C to 1, 1.5, 2, 3, 6, or 11 ms. LP3906 Default Power-Off Sequence EN_T Vout Buck1 t1 Vout Buck2 t2 Vout LDO1 t3 Vout LDO2 t4 Symbol Description Min Typ Max Units t1 Programmable Delay from EN_T deassertion to VCC_Buck1 Off 1.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com I2C DATA VALIDITY The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the data line can only be changed when CLK is LOW. SCL SDA data change allowed data valid data change allowed data valid data change allowed Figure 34. I2C Signals: Data Validity I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 start msb Chip Address lsb w ack ack from slave ack from slave ack from slave msb Register Add lsb ack msb DATA lsb ack stop ack stop SCL 1 2 3 4 5 6 7 8 9 1 2 3 ... SDA start id = K¶60 w ack addr = K¶02 DGGUHVV K¶$$ GDWD ack w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = LP3906 chip address : 0x60 Figure 37.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com INTERRUPT STATUS REGISTER (ISRA) 0X02 This register informs the user of the temperature status of the chip. D7-2 D1 D0 Name — Temp 125°C — Access — R — Data Reserved Status bit for thermal warning PMIC T>125°C 0 – PMIC Temp. < 125°C 1 – PMIC Temp.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11 This register monitors whether the Bucks and LDOs meet the voltage output specifications.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23 This register allows the user to program the output target voltage of Buck 1. D7-5 D4-0 Name — BK1_VOUT1 Access — R/W Data Reserved Buck1 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 0.80 5’h02 0.85 5’h03 0.90 5’h04 0.95 5’h05 1.00 5’h06 1.05 5’h07 1.10 5’h08 1.15 5’h09 1.20 5’h0A 1.25 5’h0B 1.30 5’h0C 1.35 5’h0D 1.40 5’h0E 1.45 5’h0F 1.50 5’h10 1.55 5’h11 1.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 BUCK 1 TARGET VOLTAGE 2 REGISTER (B1TV2) – 0X24 This register allows the user to program the output target voltage of Buck 1. D7-5 D4-0 Name — BK1_VOUT2 Access — R/W Data Reserved Buck1 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 0.80 5’h02 0.85 5’h03 0.90 5’h04 0.95 5’h05 1.00 5’h06 1.05 5’h07 1.10 5’h08 1.15 5’h09 1.20 5’h0A 1.25 5’h0B 1.30 5’h0C 1.35 5’h0D 1.40 5’h0E 1.45 5’h0F 1.50 5’h10 1.55 5’h11 1.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com BUCK 1 RAMP CONTROL REGISTER (B1RC) - 0x25 This register allows the user to program the rate of change between the target voltages of Buck 1.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29 This register allows the user to program the output target voltage of Buck 2. D7-5 D4-0 Name — BK2_VOUT1 Access — R/W Data Reserved Buck2 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 1.0 5’h02 1.1 5’h03 1.2 5’h04 1.3 5’h05 1.4 5’h06 1.5 5’h07 1.6 5’h08 1.7 5’h09 1.8 5’h0A 1.9 5’h0B 2.0 5’h0C 2.1 5’h0D 2.2 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) – 0X2A This register allows the user to program the output target voltage of Buck 2. D7-5 D4-0 Name — BK2_VOUT2 Access — R/W Data Reserved Buck2 Output Voltage (V) 5’h00 Ext Ctrl 5’h01 1.0 5’h02 1.1 5’h03 1.2 5’h04 1.3 5’h05 1.4 5’h06 1.5 5’h07 1.6 5’h08 1.7 5’h09 1.8 5’h0A 1.9 5’h0B 2.0 5’h0C 2.1 5’h0D 2.2 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.
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LP3906 www.ti.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com LDO1 CONTROL REGISTER (LDO1VCR) – 0X39 This register allows the user to program the output target voltage of LDO 1. D7-5 D4-0 Name — LDO1_OUT Access — R/W Data Reserved LDO1 Output voltage (V) 5’h00 1.0 5’h01 1.1 5’h02 1.2 5’h03 1.3 5’h04 1.4 5’h05 1.5 5’h06 1.6 5’h07 1.7 5’h08 1.8 5’h09 1.9 5’h0A 2.0 5’h0B 2.1 5’h0C 2.2 5’h0D 2.3 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.8 5’h13 2.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A This register allows the user to program the output target voltage of LDO 2. D7-5 D4-0 Name — LDO2_OUT Access — R/W Data Reserved LDO2 Output voltage (V) 5’h00 1.0 5’h01 1.1 5’h02 1.2 5’h03 1.3 5’h04 1.4 5’h05 1.5 5’h06 1.6 5’h07 1.7 5’h08 1.8 5’h09 1.9 5’h0A 2.0 5’h0B 2.1 5’h0C 2.2 5’h0D 2.3 5’h0E 2.4 5’h0F 2.5 5’h10 2.6 5’h11 2.7 5’h12 2.8 5’h13 2.
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LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com APPLICATION NOTES SYSTEM CLOCK INPUT (SYNC) PIN Pin 23 of the chip allows for a system clock input in order to synchronize the buck converters in PWM mode. This is useful if the user wishes to force the bucks to work synchronously with the system. Otherwise, the user should tie the pin to GND and the bucks will operate on an internal 2 MHz clock.
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LP3906 www.ti.com Lt SNVS456M – AUGUST 2006 – REVISED MAY 2013 §VIN - VOUT· x § VOUT· x § 1 · © IPP ¹ © VIN ¹ © f ¹ (6) Inductor LSW1,2 Value Unit 2.2 µH Description SW1,2 inductor Notes D.C.R. 70 mΩ External Capacitors The regulators on the LP3906 require external capacitors for regulator stability. These are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance.
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LP3906 www.ti.com CAP VALUE (% of NOMINAL 1 PF) SNVS456M – AUGUST 2006 – REVISED MAY 2013 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 39. Graph Showing a Typical Variation in Capacitance vs. DC Bias As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications table.
PAGE 39
LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 Output Capacitor Selection for SW1, SW2 A 10 µF, 6.3V ceramic capacitor should be used on the output of the sw1 and sw2 magnetic dc/dc converters. The output capacitor needs to be mounted as close as possible to the output of the device. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used.
PAGE 40
LP3906 SNVS456M – AUGUST 2006 – REVISED MAY 2013 www.ti.com The I2C Chip ID address is offered as a metal mask option. The current value equals 0x60. MODE BOUNCE PFM-PWM transition at low load current. To improve efficiency at lower load currents LP3906 buck converters employ an automatically invoked PFM mode for the low load operation. The PFM mode operates with a much lower value quiescent current (IQ) than the PWM mode of operation that is used in the higher load currents.
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LP3906 www.ti.com SNVS456M – AUGUST 2006 – REVISED MAY 2013 REVISION HISTORY Changes from Revision L (May 2013) to Revision M • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3906SQ-DJXI/NOPB WQFN NHZ 24 1000 178.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 LP3906SQ-FXPI/NOPB WQFN NHZ 24 1000 178.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 LP3906SQ-JXXI/NOPB WQFN NHZ 24 1000 178.0 12.4 4.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3906SQ-DJXI/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0 LP3906SQ-FXPI/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0 LP3906SQ-JXXI/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0 LP3906SQ-PPXP/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0 LP3906SQ-TKXII/NOPB WQFN NHZ 24 1000 210.0 185.0 35.
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MECHANICAL DATA NHZ0024B SQA24B (Rev A) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.