Datasheet

LP38858
www.ti.com SNVS462D –OCTOBER 2006–REVISED APRIL 2013
Soft-Start Time = C
SS
× r
SS
× 5 (1)
Since the V
OUT
rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ),
and V
OUT
will require four additional time constants (4τ) to reach the final value (5τ) .
After achieving normal operation, should V
BIAS
fall below the ULVO threshold the device output will be disabled
and the Soft-Start capacitor (C
SS
) discharge circuit will become active. The C
SS
discharge circuit will remain
active until V
BIAS
falls to 500 mV (typical). When V
BIAS
falls below 500 mV (typical), the C
SS
discharge circuit will
cease to function due to a lack of sufficient biasing to the control circuitry.
Since V
REF
appears on the SS pin, any leakage through C
SS
will cause V
REF
to fall, and thus affect V
OUT
. A
leakage of 50 nA (about 10 MΩ) through C
SS
will cause V
OUT
to be approximately 0.1% lower than nominal, while
a leakage of 500 nA (about 1 MΩ) will cause V
OUT
to be approximately 1% lower than nominal. Typical ceramic
capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient
temperature must be included in the capacitor selection process.
Typical C
SS
values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs
to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100
nF will provide soft-start, but may not be fully discharged if V
BIAS
falls from the UVLO threshold to less than 500
mV in less than 100 µs.
Figure 27 shows the relationship between the C
OUT
value and a typical C
SS
value.
Figure 27. Typical C
SS
vs C
OUT
Values
The C
SS
capacitor must be connected to a clean ground path back to the device ground pin. No components,
other than C
SS
, should be connected to the SS pin, as there could be adverse effects to V
OUT
.
If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value
is always recommended.
POWER DISSIPATION AND HEAT-SINKING
Additional copper area for heat-sinking may be required depending on the maximum device dissipation (P
D
) and
the maximum anticipated ambient temperature (T
A
) for the device. Under all possible conditions, the junction
temperature must be within the range specified under operating conditions.
The total power dissipation of the device is the sum of three different points of dissipation in the device.
The first part is the power that is dissipated in the NMOS pass element, and can be determined with the
formula:
P
D(PASS)
= (V
IN
- V
OUT
) × I
OUT
(2)
The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the
formula:
P
D(BIAS)
= V
BIAS
× I
GND(BIAS)
where
• I
GND(BIAS)
is the portion of the operating ground current of the device that is related to V
BIAS
(3)
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