Datasheet

LP38853
www.ti.com SNVS335D –DECEMBER 2006–REVISED APRIL 2013
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F
Z
pole set by R1 and
C
FF
.
( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ (6)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for C
FF
, for a range of V
OUT
values. Other values of R1, R2, and C
FF
are available that will give
similar results.
Table 1.
V
OUT
R1 R2 C
FF
F
Z
0.8V 1.07 kΩ 1.78 kΩ 12 nF 12.4 kHz
0.9V 1.50 kΩ 1.87 kΩ 8.2 nF 12.9 kHz
1.0V 1.00 kΩ 1.00 kΩ 12 nF 13.3 kHz
1.1V 1.65 kΩ 1.37 kΩ 8.2 nF 11.8 kHz
1.2V 1.40 kΩ 1.00 kΩ 10 nF 11.4 kHz
1.3V 1.15 kΩ 715 Ω 12 nF 11.5 kHz
1.4V 1.07 kΩ 590 Ω 12 nF 12.4 kHz
1.5V 2.00 kΩ 1.00 kΩ 6.8 nF 11.7 kHz
1.6V 1.65 kΩ 750 Ω 8.2 nF 11.8 kHz
1.7V 2.55 kΩ 1.07 kΩ 5.6 nF 11.1 kHz
1.8V 2.94 kΩ 1.13 kΩ 4.7 nF 11.5 kHz
Please refer to the TI AN-1378 Application Report for additional information on how resistor tolerances affect the
calculated V
OUT
value.
INPUT VOLTAGE
The input voltage (V
IN
) is the high current external voltage rail that will be regulated down to a lower voltage,
which is applied to the load. The input voltage must be at least V
OUT
+ V
DO
, and no higher than whatever value is
used for V
BIAS
.
For applications where V
BIAS
is higher than 4.5V, V
IN
must be no greater than 4.5V, otherwise output voltage
accuracy may be affected.
BIAS VOLTAGE
The bias voltage (V
BIAS
) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. When V
OUT
is set to 1.20V, or less, V
BIAS
may be anywhere in the
operating range of 3.0V to 5.5V. If V
OUT
is set higher than 1.20V , V
BIAS
must be between 4.5V and 5.5V to
ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.
As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the
device will be functional, but the operating parameters will not be within the specified limits.
SUPPLY SEQUENCING
There is no requirement for the order that V
IN
or V
BIAS
are applied or removed.
One practical limitation is that the Soft-Start circuit starts charging C
SS
when both V
BIAS
rises above the UVLO
threshold and the Enable pin is above the V
EN(ON)
threshold. If the application of V
IN
is delayed beyond this point
the benefits of Soft-Start will be compromised.
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