Datasheet

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R2
R1
1x= VV
ADJOUT
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LP38852
SNVS482E –JANUARY 2007–REVISED APRIL 2013 www.ti.com
Feed Forward Capacitor, C
FF
(Refer to the Typical Application Circuit)
When using a ceramic capacitor for C
OUT
, the typical ESR value will be too small to provide any meaningful
positive phase compensation, F
Z
, to offset the internal negative phase shifts in the gain loop.
F
Z
= (1 / (2 x π x C
OUT
x ESR) ) (1)
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient
response of the device. This capacitor, C
FF
, in parallel with R1, will form a zero in the loop response given by the
formula:
F
Z
= (1 / (2 x π x C
FF
x R1) ) (2)
For optimum load transient response select C
FF
so the zero frequency, F
Z
, falls between 10 kHz and 15 kHz.
(C
FF
= (1 / (2 x π x R1 x F
Z
) (3)
The phase lead provided by C
FF
diminishes as the DC gain approaches unity, or V
OUT
approaches V
ADJ
. This is
because C
FF
also forms a pole with a frequency of:
F
P
= (1 / (2 x π x C
FF
x (R1 || R2) ) ) (4)
It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far
apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The
phase lead provided from C
FF
diminishes quickly as the output voltage is reduced, and has no effect when V
OUT
= V
ADJ
. For this reason, relying on this compensation technique alone is adequate only for higher output
voltages. For the LP38852, the practical minimum V
OUT
is 0.8V when a ceramic capacitor is used for C
OUT
.
Figure 31. F
ZERO
and F
POLE
vs Gain
SETTING THE OUTPUT VOLTAGE
(Refer to the Typical Application Circuit)
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
(5)
The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of V
ADJ
is ensured, the use of low quality
resistors for R1 and R2 can easily produce a V
OUT
value that is unacceptable.
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F
Z
pole set by R1 and
C
FF
.
( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ (6)
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