Datasheet

LP38851
SNVS492C –JUNE 2007–REVISED APRIL 2013 www.ti.com
Please refer to Application Note AN-1378 (SNVA112) for additional information on how resistor tolerances affect
the calculated V
OUT
value.
INPUT VOLTAGE
The input voltage (V
IN
) is the high current external voltage rail that will be regulated down to a lower voltage,
which is applied to the load. The input voltage must be at least V
OUT
+ V
DO
, and no higher than whatever value is
used for V
BIAS
.
For applications where V
BIAS
is higher than 4.5V, V
IN
must be no greater than 4.5V, otherwise output voltage
accuracy may be affected.
BIAS VOLTAGE
The bias voltage (V
BIAS
) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. When V
OUT
is set to 1.20V, or less, V
BIAS
may be anywhere in the
operating range of 3.0V to 5.5V. If V
OUT
is set higher than 1.20V , V
BIAS
must be between 4.5V and 5.5V to
ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.
As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the
device will be functional, but the operating parameters will not be within the specified limits.
SUPPLY SEQUENCING
There is no requirement for the order that V
IN
or V
BIAS
are applied or removed.
One practical limitation is that the Soft-Start circuit starts charging C
SS
when both V
BIAS
rises above the UVLO
threshold and the Enable pin is above the V
EN(ON)
threshold. If the application of V
IN
is delayed beyond this point
the benefits of Soft-Start will be compromised.
In any case, the output voltage cannot be specified until both V
IN
and V
BIAS
are within the range of specified
operating values.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin
must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when V
IN
is abruptly taken low and C
OUT
continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there will not be any reverse current flow through the pass element during a reverse
voltage event. The gate of the pass element is not driven when V
BIAS
is below the UVLO threshold, or when the
Enable pin is held low.
When V
BIAS
is above the UVLO threshold, and the Enable pin is above the V
EN(ON)
threshold, the control circuitry
is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the
control circuit will drive the gate of the pass element to the full V
BIAS
potential when the output voltage begins to
fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the R
DS(ON)
of
the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this
manner will not damage the device as the current will rapidly decay. However, continuous reverse current should
be avoided.
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LP38851