Datasheet

+
R2
R1
1x= VV
ADJOUT
¸
¹
·
¨
©
§
¸
©
§
¨ ¨
¹
·
LP38851
www.ti.com SNVS492C –JUNE 2007–REVISED APRIL 2013
Figure 30. F
ZERO
and F
POLE
vs Gain
SETTING THE OUTPUT VOLTAGE
(Refer to TYPICAL APPLICATION CIRCUIT)
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
(5)
The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature
coefficients. It is important to remember that, although the value of V
ADJ
is specified, the use of low quality
resistors for R1 and R2 can easily produce a V
OUT
value that is unacceptable.
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F
Z
pole set by R1 and
C
FF
.
( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ (6)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for C
FF
, for a range of V
OUT
values. Other values of R1, R2, and C
FF
are available that will give
similar results.
Table 1.
V
OUT
R1 R2 C
FF
F
Z
0.8V 1.07 kΩ 1.78 kΩ 220 pF 676 kHz
0.9V 1.50 kΩ 1.87 kΩ 180 pF 589 kHz
1.00V 1.00 kΩ 1.00 kΩ 270 pF 589 kHz
1.1V 1.65 kΩ 1.37 kΩ 150 pF 643 kHz
1.2V 1.40 kΩ 1.00 kΩ 180 pF 631 kHz
1.3V 1.15 kΩ 715 Ω 220 pF 629 kHz
1.4V 1.07 kΩ 590 Ω 220 pF 676 kHz
1.5V 2.00 kΩ 1.00 kΩ 120pF 663 kHz
1.6V 1.65 kΩ 750 Ω 150 pF 643 kHz
1.7V 2.55 kΩ 1.07 kΩ 100 pF 624 kHz
1.8V 2.94 kΩ 1.13 kΩ 82 pF 660 kHz
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LP38851