Datasheet

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LP38851

www.ti.com

SNVS492C –JUNE 2007–REVISED APRIL 2013

LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator with

Enable and Soft-Start

Check for Samples: LP38851

FEATURES

DESCRIPTION

The LP38851-ADJ is a high current, fast response

• Adjustable V

OUT

Range of 0.80V to 1.8V

regulator which can maintain output voltage

• Wide V

BIAS

Supply Operating Range of 3.0V to

regulation with extremely low input to output voltage

5.5V

drop. Fabricated on a CMOS process, the device

• Stable with 10µF Ceramic Capacitors

operates from two input voltages: V

BIAS

provides

voltage to drive the gate of the N-MOS power

• Dropout Voltage of 115 mV (Typical) at 800 mA

transistor, while V

is the input voltage which

Load Current

supplies power to the load. The use of an external

• Precision V

ADJ

across All Line and Load

bias rail allows the part to operate from ultra low V

Conditions:

voltages. Unlike bipolar regulators, the CMOS

architecture consumes extremely low quiescent

– ±1.5% V

ADJ

for T

= 25°C

current at any output load current. The use of an N-

– ±2.0% V

ADJ

for 0°C ≤ T

≤ +125°C

MOS power transistor results in wide bandwidth, yet

– ±3.0% V

ADJ

for -40°C ≤ T

≤ +125°C

minimum external capacitance is required to maintain

• Over-Temperature and Over-Current loop stability.

Protection

The fast transient response of this device makes it

• Available in 8-Lead SO PowerPad,

suitable for use in powering DSP, Microcontroller

7-Lead SFM and 7-Lead PFM Packages

Core voltages and Switch Mode Power Supply post

regulators. The part is available in PSOP 8–pin, SFM

• −40°C to +125°C Operating Junction

7–pin, and TO-263 7-pin packages.

Temperature Range

• Dropout Voltage: 115 mV (typical) at 800 mA

load current

APPLICATIONS

• Low Ground Pin Current: 10 mA (typical) at 800

• ASIC Power Supplies in:

mA load current

– Desktops, Notebooks, and Graphics Cards,

• Soft-Start: Programmable Soft-Start time

Servers

• Precision ADJ Voltage: ±1.5% for T

= 25°C,

– Gaming Set Top Boxes, Printers and

and ±2.0% for 0°C ≤ T

≤ +125°C, across all line

Copiers

and load conditions

• Server Core and I/O Supplies

• DSP and FPGA Power Supplies

• SMPS Post-Regulator

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 LP38851 800 mA Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start Check for Samples: LP38851 FEATURES DESCRIPTION • • The LP38851-ADJ is a high current, fast response regulator which can maintain output voltage regulation with extremely low input to output voltage drop.
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LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION CIRCUIT LP38851-ADJ VIN IN VBIAS VOUT OUT CIN 10 PF Ceramic CFF R1 BIAS CBIAS 1 PF VEN SS COUT 10 PF Ceramic ADJ EN R2 GND CSS GND GND Connection Diagram 1 2 3 4 5 6 7 TAB IS GND LP38851S-ADJ SS EN IN GND ADJ OUT BIAS 7 IN BIAS 3 6 EN GND 4 5 SS Figure 3. 8-Lead SO PowerPad - Top View See DDA Package TAB IS GND LP38851T-ADJ 1 2 3 4 5 6 7 8 N/C DAP Connect to GND Figure 1.
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LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) SFM Pin # PFM Pin # SO PowerPad Pin # Pin Symbol - - DAP DAP Pin Description The SO PowerPad DAP is a thermal connection only that is physically attached to the backside of the die, and used as a thermal heat-sink connection. See APPLICATION INFORMATION for details. These devices have limited built-in ESD protection.
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LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
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LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
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LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. 6 VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature Figure 4. Figure .
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LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. VOUT vs Temperature VOUT vs VIN Figure 9. Figure 10. UVLO Thresholds vs Temperature Soft-Start rSS Variation vs Temperature Figure 11.
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LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. 8 Enable Pull-Down Current (IEN) vs Temperature Enable Pull-Up Resistor (rEN) vs Temperature Figure 15. Figure 16.
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LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. Load Transient Response, COUT = 10 µF Ceramic Load Transient Response, COUT = 10 µF Ceramic Figure 21. Figure 22.
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LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Refer to the TYPICAL APPLICATION CIRCUIT. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 180 pF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, , CSS = Open. VBIAS PSRR VIN PSRR Figure 27. Figure 28. Output Noise Figure 29.
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LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 BLOCK DIAGRAM OUT IN LP38851-ADJ BIAS Under-Voltage Lock-Out Thermal Shut Down rEN ADJ EN Enable 1.2V rSS SS VREF ILIMIT GND 0.
PAGE 12
LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in TYPICAL APPLICATION CIRCUIT. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be increased without limit.
PAGE 13
LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 Figure 30. FZERO and FPOLE vs Gain SETTING THE OUTPUT VOLTAGE (Refer to TYPICAL APPLICATION CIRCUIT) The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: § § R1 ·· VOUT = VADJ x ¨1 + ¨ ¸¨ © © R2 ¹¹ (5) The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature coefficients.
PAGE 14
LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com Please refer to Application Note AN-1378 (SNVA112) for additional information on how resistor tolerances affect the calculated VOUT value. INPUT VOLTAGE The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. For applications where VBIAS is higher than 4.
PAGE 15
LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 SOFT-START The LP38851 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor (COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin. The soft-start timing capacitor (CSS) is internally held to ground until both VBIAS rises above the Under-Voltage Lock-Out threshold (ULVO) and the Enable pin is higher than the VEN(ON) threshold.
PAGE 16
LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com ENABLE OPERATION The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has an internal pull-up, through a typical 160 kΩ resistor, to VBIAS. If the Enable pin is actively driven, pulling the Enable pin above the VEN threshold of 1.25V (typical) will turn the regulator output on, while pulling the Enable pin below the VEN threshold will turn the regulator output off.
PAGE 17
LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 T H d T J - (T C + T J ) A A H C where • • θJA is the required total thermal resistance from the junction to the ambient air, θCH is the thermal resistance from the case to the surface of the heart-sink θJC is the thermal resistance from the junction to the surface of the case (14) For this equation, θJC is about 3°C/W for a SFM package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.
PAGE 18
LP38851 SNVS492C – JUNE 2007 – REVISED APRIL 2013 www.ti.com Heat-Sinking The SO PowerPad Package The LP38851MR package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W. The θJA rating of 168°C/W includes the device DAP soldered to an area of 0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper, with no airflow. Figure 34.
PAGE 19
LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38851MRX-ADJ/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP38851SX-ADJ/NOPB DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.75 14.85 5.0 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38851MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP38851SX-ADJ/NOPB DDPAK/TO-263 KTW 7 500 367.0 367.0 45.
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MECHANICAL DATA NDZ0007B TA07B (Rev E) www.ti.
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MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.
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MECHANICAL DATA KTW0007B TS7B (Rev E) BOTTOM SIDE OF PACKAGE www.ti.
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