Datasheet

V
REF
+
-
+
V
IN
V
OUT
UVLO
S/D
GND
Vbias
ADJ
GND
INPUT
SHUTDOWN
1
2
3
4
8
7
6
5
BIAS
GND
OUTPUT
ADJ
N/C
DAP
LP38841-ADJ
SNVS305C –FEBRUARY 2005–REVISED APRIL 2013 www.ti.com
Connection Diagram
Figure 1. SO-8 – Top View
PIN DESCRIPTION
Pin Pin Pin
Number Name Description
The Adjust pin is used to set the regulated output voltage by connecting it to the external
1 ADJ
resistors R1 and R2 (see Typical Application Circuit).
2 OUTPUT The regulated output voltage is connected to this pin.
The Bias pin is used to provide the low current bias voltage to the chip which operates the
3 BIAS
internal circuitry and provides drive voltage for the N-FET.
4, 5 GND These are the power and analog grounds for the IC. Connect both pins to ground.
This provides a low power shutdown function which turns the regulated output OFF. Tie to
6 SHUTDOWN
V
BIAS
if this function is not used.
The high current input voltage which is regulated down to the nominal output voltage must be
7 INPUT connected to this pin. Because the bias voltage to operate the chip is provided separately, the
input voltage can be as low as a few hundred millivolts above the output voltage.
8 N/C This pin is floating, it has no internal connection.
The SO DAP is a thermal connection that is physically connected to the backside of the die,
DAP DAP and is used as a thermal connection to the PC Board copper. The DAP is not a ground pin
connection, but should be connected to ground potential.
Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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