Datasheet

LP3878-ADJ
SNVS311B –MAY 2005–REVISED APRIL 2013 www.ti.com
FEEDFORWARD CAPACITOR
The feedforward capacitor designated C
FF
in the Basic Application circuit is required to increase phase margin
and assure loop stability. Improved phase margin also gives better transient response to changes in load or input
voltage, and faster settling time on the output voltage when transients occur. C
FF
forms both a pole and zero in
the loop gain, the zero providing beneficial phase lead (which increases phase margin) and the pole adding
undesirable phase lag (which should be minimized). The zero frequency is determined both by the value of C
FF
and R1:
fz = 1 / (2 x π x C
FF
x R1) (1)
The pole frequency resulting from C
FF
is determined by the value of C
FF
and the parallel combination of R1 and
R2:
fp = 1 / (2 x π x C
FF
x (R1 // R2)) (2)
At higher output voltages where R1 is much greater than R2, the value of R2 primarily determines the value of
the parallel combination of R1 // R2. This puts the pole at a much higher frequency than the zero. As the
regulated output voltage is reduced (and the value of R1 decreases), the parallel effect of R2 diminishes and the
two equations become equal (at which point the pole and zero cancel out). Because the pole frequency gets
closer to the zero at lower output voltages, the beneficial effects of C
FF
are increased if the frequency range of
the zero is shifted slightly higher for applications with low Vout (because then the pole adds less phase lag at the
loop's crossover frequency).
C
FF
should be selected to place the pole zero pair at a frequency where the net phase lead added to the loop at
the crossover frequency is maximized. The following design guidelines were obtained from bench testing to
optimize phase margin, transient response, and settling time:
For Vout ≤ 2.5V: C
FF
should be selected to set the zero frequency in the range of about 50 kHz to 200 kHz.
For Vout > 2.5V: C
FF
should be selected to set the zero frequency in the range of about 20 kHz to 100 kHz.
CAPACITOR CHARACTERISTICS
CERAMIC:
The LP3878-ADJ was designed to work with ceramic capacitors on the output to take advantage of the benefits
they offer: for capacitance values in the 10 µF range, ceramics are the least expensive and also have the lowest
ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 10 µF ceramic
capacitor is in the range of 5 mΩ to 10 mΩ, which meets the ESR limits required for stability by the LP3878-ADJ.
One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Many large value
ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in
the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.
Another significant problem with Z5U and Y5V dielectric devices is that the capacitance drops severely with
applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated
voltage applied to it.
For these reasons, X7R and X5R type ceramic capacitors must be used on the input and output of the
LP3878-ADJ.
SHUTDOWN INPUT OPERATION
The LP3878-ADJ is shut off by pulling the Shutdown input low, and turned on by pulling it high. If this feature is
not to be used, the Shutdown input should be tied to V
IN
to keep the regulator output on at all times.
To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and
below the specified turn-on/turn-off voltage thresholds listed in the Electrical Characteristics section under
V
ON/OFF
.
REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the LP3878-ADJ has an inherent diode connected
between the regulator output and input.
During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.
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