Datasheet

1 2
3
4
5
SD
V
IN
V
OUT
ADJ
GND
LP3875-ADJ
SNVS247D –SEPTEMBER 2003–REVISED APRIL 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
Figure 1. TO-220-5 Package (Top View) Figure 2. DDPAK/TO-263-5 Package (Top View)
Bent, Staggered Leads
Figure 3. SOT-223-5 Package (Top View)
Table 1. PIN DESCRIPTION for TO-220-5 and DDPAK/TO-263-5 Packages
LP3875-ADJ
Pin #
Name Function
1 SD Shutdown
2 V
IN
Input Supply
3 GND Ground
4 V
OUT
Output Voltage
5 ADJ Set Output Voltage
Table 2. PIN DESCRIPTION for SOT-223-5 Package
LP3875-ADJ
Pin #
Name Function
1 SD Shutdown
2 V
IN
Input Supply
3 V
OUT
Output Voltage
4 ADJ Set Output Voltage
5 GND Ground
2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3875-ADJ