Datasheet
LP3470
SNVS003F –JUNE 1999–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)
V
CC
Voltage −0.3V to +6V
Reset Voltage −0.3V to +6V
Output Current (Reset) 10 mA
Operating Temperature Range LP3470 −20°C to +85°C
LP3470I −40°C to +85°C
Junction Temperature (T
Jmax
) 125°C
Power Dissipation (T
A
= 25°C)
(3)
300 mW
θ
JA
(3)
280°C/W
Storage Temp. Range −65°C to +150°C
Lead Temp. (Soldering, 5 sec) 260°C
ESD Rating
(4)
2 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when
operating the device beyond its operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
(Maximum Junction Temperature),
θ
JA
(Junction to Ambient Thermal Resistance), and T
A
(Ambient Temperature). The maximum allowable power dissipation at any
temperature is P
Dmax
= (T
Jmax
− T
A
)/ θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower.
(4) The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Electrical Characteristics
Limits in standard typeface are for T
J
= 25°C, and limits in boldface type apply over the full operating temperature range,
unless otherwise specified. V
CC
= +2.4V to +5.0V unless otherwise noted.
Symbol Parameter Conditions Typ
(1)
Min
(2)
Max
(2)
Units
V
CC
Operating Voltage Range 0.5 5.5 V
I
CC
V
CC
Supply Current V
CC
= 4.5V 16 30 µA
V
RTH
Reset Threshold Voltage
(3)
LP3470 V
RTH
0.99 1.01
V
RTH
V
RTH
0.99 1.01
V
RTH
V
RTH
V
LP3470I V
RTH
0.99 1.01
V
RTH
V
RTH
0.985 1.015
V
RTH
V
RTH
V
HYST
Hysteresis Voltage
(4)
35 15 65 mV
t
PD
V
CC
to Reset Delay V
CC
falling at 1 mV/µs 100 300 µs
t
RP
Reset Timeout Period
(5)
C
1
= 1 nF 2 1.0 3.5 ms
V
OL
Reset Output Voltage Low V
CC
= 0.5V; I
OL
= 30 µA 0.1
V
CC
= 1.0V; I
OL
= 100 µA 0.1 V
V
CC
=V
RTH
−100 mV; I
OL
= 4 mA 0.4
R
1
External Pull-up Resistor 20 0.68 68 kΩ
I
LEAK
Reset Output Leakage Current 0.15 1
µA
6
(1) Typical numbers are at 25°C and represent the most likely parametric norm.
(2) Min. and Max. limits in standard typeface are 100% production tested at 25°C. Min. and Max. limits in boldface are ensured through
correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level
(AOQL).
(3) Factory-trimmed reset thresholds are available in 50 mV increments from 2.4V to 5.0V. Contact your TI representative.
(4) V
HYST
affects the relation between V
CC
and Reset as shown in the timing diagram.
(5) t
RP
is programmable by varying the value of the external capacitor (C
1
) connected to pin SRT. The equation is: t
RP
= 2000 x C
1
(C
1
in
µF and t
RP
in ms).
2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP3470