Datasheet

V
TT
V
REF
V
DD
R
S
R
T
CHIPSET
MEMORY
-
+
V
TT
PV
IN
V
DDQ
SD
GND
AV
IN
V
SENSE
50k
50k
+
-
V
REF
LP2998/LP2998-Q1
www.ti.com SNVS521J –DECEMBER 2007–REVISED DECEMBER 2013
Block Diagram
DETAILED DESCRIPTION
The LP2998 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and
SSTL-18. The output, V
TT
is capable of sinking and sourcing current while regulating the output voltage equal to
VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot
through. The LP2998 also incorporates two distinct power rails that separates the analog circuitry from the power
output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits
the LP2998 to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). The
LP2998 can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting
at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single
parallel termination. This involves one R
S
series resistor from the chipset to the memory and one R
T
termination
resistor. Typical values for R
S
and R
T
are 25 Ohms, although these can be changed to scale the current
requirements from the LP2998. This implementation can be seen below in Figure 17.
Figure 17. SSTL-Termination Scheme
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