Datasheet

V
TT
LP2997
PV
IN
V
DD
Q
V
REF
AV
IN
V
REF
= 0.9V
V
SENSE
GND
+
+
+
AV
IN
= 2.5V
V
TT
= 0.9V
SD
SD
V
DD
Q
= 1.8V
7P
F
0.01 PF
P
22
0
F
LP2997
SNVS295F –MAY 2004–REVISED APRIL 2013 www.ti.com
Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an
internal ground plane. Using larger traces and more copper on the top side of the board can also help. With
careful layout it is possible to reduce the θ
JA
further than the nominal values shown in Figure 13.
Optimizing the θ
JA
and placing the LP2997 in a section of a board exposed to lower ambient temperature allows
the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing
the three main sources of loss: output current at V
TT
, either sinking or sourcing, and quiescent current at AVIN
and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation can be
calculated from the following equations:
P
D
= P
AVIN
+ P
VDDQ
+ P
VTT
(3)
Where,
P
AVIN
= I
AVIN
* V
AVIN
(4)
P
VDDQ
= V
VDDQ
* I
VDDQ
= V
VDDQ
2
x R
VDDQ
(5)
To calculate the maximum power dissipation at V
TT
both conditions at V
TT
need to be examined, sinking and
sourcing current. Although only one equation will add into the total, V
TT
cannot source and sink current
simultaneously.
P
VTT
= V
VTT
x I
LOAD
(Sinking) or (6)
P
VTT
= ( V
PVIN
- V
VTT
) x I
LOAD
(Sourcing) (7)
The power dissipation of the LP2997 can also be calculated during the shutdown state. During this condition the
output V
TT
will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any
current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN
and the constant impedance that is seen at the VDDQ pin.
P
D
= P
AVIN
+ P
VDDQ
(8)
P
AVIN
= I
AVIN
x V
AVIN
(9)
P
VDDQ
= V
VDDQ
* I
VDDQ
= V
VDDQ
2
x R
VDDQ
(10)
Typical Application Circuits
Several different application circuits have been shown to illustrate some of the options that are possible in
configuring the LP2997. Graphs of the individual circuit performance can be found in the Typical Performance
Characteristics section in the beginning of the datasheet. These curves illustrate how the maximum output
current is affected by changes in AVIN and PVIN.
Figure 14 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to
the 1.8V rail and the AVIN pin can be connected to either a 2.5V, 3.3V or 5V rail.
This circuit permits termination in a minimum amount of board space and component count. Capacitor selection
can be varied depending on the number of lines terminated and the maximum load transient. However, with
motherboards and other applications where V
TT
is distributed across a long plane it is advisable to use multiple
bulk capacitors and addition to high frequency decoupling. The bulk output capacitors should be situated at both
ends of the V
TT
plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR
and low cost.
Figure 14. Recommended DDR-II Termination
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